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Device Features
Fully Qualified Bluetooth v1.2 system Enhanced Data Rate (EDR) compliant with v0.9 of specification for both 2Mbps and 3Mbps modulation modes Full Speed Bluetooth Operation with Full Piconet Support Scatternet Support www..com 1.8V core, 1.8 to 3.6V I/O Low Power 1.8V Operation Small footprint 8 x 8mm 96-ball VFBGA Package Also available in 6 x 6mm package option Minimum External Components Integrated 1.8V regulator USB and Dual UART Ports Support for 802.11 Coexistence Support for 8Mbit External Flash RoHS Compliant
_aiEceEQJbniEea~a
Single Chip Bluetooth(R) v1.2 System with EDR
Pre-Production Information Datasheet For
BC417143B-ES-IQN BC417143B-ES-IRN September 2004
General Description
_aiEceEQJbniEea~a is a single chip radio and baseband IC for Bluetooth 2.4GHz systems including enhanced data rates (EDR) to 3Mbps. BC417143B interfaces to 8Mbit of external Flash memory. When used with the CSR Bluetooth software stack, it provides a fully compliant Bluetooth system to v1.2 of the specification for data and voice communications.
External Memory RAM FLASH
Applications
PCs Personal Digital Assistants (PDAs) Computer Accessories (compact Flash Cards, PCMCIA Cards, SD Cards and USB Dongles) Access Points Digital Cameras BlueCore4-External has been designed to reduce the number of external components required which ensures production costs are minimised. The device incorporates auto-calibration and built-in self-test (BIST) routines to simplify development, type approval and production test. All hardware and device firmware is fully compliant with the Bluetooth v1.2 Specification (all mandatory and optional features). To improve the performance of both Bluetooth and 802.11b/g co-located systems a wide range of co-existence features are available including two types of hardware signalling: basic activity signalling and Intel WCS activity & channel signalling
SPI
RF IN RF OUT
2.4 GHz Radio
Baseband DSP
I/O
UART/USB
PIO
MCU PCM
XTAL
BlueCore4-External System Architecture
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Status Information
Contents
Status Information ................................................................................................................................................ 7 1 2 Key Features .................................................................................................................................................. 8 8 x 8mm VFBGA Package Information ......................................................................................................... 9 2.1 BlueCore4-External Pinout Diagram........................................................................................................ 9 2.2 Device Terminal Functions (BC417143B-ES-IQN) ................................................................................ 10 3 6 x 6mm VFBGA Package Information ....................................................................................................... 15 3.1 BlueCore4-External 6 x 6mm Pinout Diagram ....................................................................................... 15
_aiEceEQJbniEea~a Product Data Sheet
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Device Terminal Functions (BC417143B-ES-IRN) ................................................................................ 16
4 5
Electrical Characteristics ............................................................................................................................ 21 Radio Characteristics - Basic Data Rate ................................................................................................... 25 5.1 Temperature +20C ............................................................................................................................... 25 5.1.1 Transmitter................................................................................................................................. 25 5.1.2 Receiver..................................................................................................................................... 26 5.2 Temperature -40C................................................................................................................................ 27 5.2.1 Transmitter................................................................................................................................. 27 5.2.2 Receiver..................................................................................................................................... 27 5.3 Temperature -25C................................................................................................................................ 28 5.3.1 Transmitter................................................................................................................................. 28 5.3.2 Receiver..................................................................................................................................... 28 5.4 Temperature +85C ............................................................................................................................... 29 5.4.1 Transmitter................................................................................................................................. 29 5.4.2 Receiver..................................................................................................................................... 29 5.5 Temperature +105C ............................................................................................................................. 30 5.5.1 Transmitter................................................................................................................................. 30 5.5.2 Receiver..................................................................................................................................... 30 5.6 Power Consumption .............................................................................................................................. 31
6
Radio Characteristics - Enhanced Data Rate............................................................................................ 32 6.1 Temperature +20C ............................................................................................................................... 32 6.1.1 Transmitter................................................................................................................................. 32 6.1.2 Receiver..................................................................................................................................... 33 6.2 Temperature -40C................................................................................................................................ 34 6.2.1 Transmitter................................................................................................................................. 34 6.2.2 Receiver..................................................................................................................................... 34 6.3 Temperature -25C................................................................................................................................ 35 6.3.1 Transmitter................................................................................................................................. 35 6.3.2 Receiver..................................................................................................................................... 35 6.4 Temperature +85C ............................................................................................................................... 36 6.4.1 Transmitter................................................................................................................................. 36 6.4.2 Receiver..................................................................................................................................... 36 6.5 Temperature +105C ............................................................................................................................. 37 6.5.1 Transmitter................................................................................................................................. 37 6.5.2 Receiver..................................................................................................................................... 37 Device Diagram ........................................................................................................................................... 38 Description of Functional Blocks ............................................................................................................... 39 8.1 RF Receiver........................................................................................................................................... 39 8.1.1 Low Noise Amplifier ................................................................................................................... 39 8.1.2 Analogue to Digital Converter .................................................................................................... 39 8.2 RF Transmitter....................................................................................................................................... 39 8.2.1 IQ Modulator .............................................................................................................................. 39 8.2.2 Power Amplifier .......................................................................................................................... 39 8.3 RF Synthesiser ...................................................................................................................................... 39
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8.4 Clock Input and Generation ................................................................................................................... 39 8.5 Baseband and Logic.............................................................................................................................. 40 8.5.1 Memory Management Unit......................................................................................................... 40 8.5.2 Burst Mode Controller ................................................................................................................ 40 8.5.3 Physical Layer Hardware Engine DSP....................................................................................... 40 8.5.4 RAM ........................................................................................................................................... 40 8.5.5 External Memory Driver ............................................................................................................. 40 8.5.6 USB............................................................................................................................................ 40 8.5.7 Synchronous Serial Interface ..................................................................................................... 41 8.5.8 UART ......................................................................................................................................... 41 8.5.9 Audio PCM Interface .................................................................................................................. 41 8.6 Microcontroller ....................................................................................................................................... 41 8.6.1 Programmable I/O...................................................................................................................... 41 www..com 8.6.2 802.11 Coexistence Interface .................................................................................................... 41 9 CSR Bluetooth Software Stacks ................................................................................................................. 42 9.1 BlueCore HCI Stack ............................................................................................................................. 42 9.1.1 Key Features of the HCI Stack - Standard Bluetooth Functionality............................................ 43 9.1.2 Key Features of the HCI Stack - Extra Functionality .................................................................. 44 9.2 BlueCore RFCOMM Stack .................................................................................................................... 46 9.2.1 Key Features of the BlueCore4-External RFCOMM Stack......................................................... 47 9.3 BlueCore Virtual Machine Stack ........................................................................................................... 48 9.4 BlueCore HID Stack ............................................................................................................................. 49 9.5 BCHS Software ..................................................................................................................................... 50 9.6 Additional Software for Other Embedded Applications .......................................................................... 50 9.7 CSR Development Systems .................................................................................................................. 50 10 Enhanced Data Rate .................................................................................................................................... 51 10.1 Enhanced Data Rate Baseband ............................................................................................................ 51 10.2 Enhanced Data Rate /4 DQPSK.......................................................................................................... 51 10.3 Enhanced Data Rate 8DPSK................................................................................................................. 52 11 Device Terminal Descriptions..................................................................................................................... 53 11.1 RF Ports ................................................................................................................................................ 53 11.1.1 TX_A and TX_B ......................................................................................................................... 53 11.1.2 Single-Ended Input (RF_IN)....................................................................................................... 54 11.2 External Reference Clock Input (XTAL_IN) ........................................................................................... 55 11.2.1 External Mode ............................................................................................................................ 55 11.2.2 XTAL_IN Impedance in External Mode ...................................................................................... 55 11.2.3 Clock Timing Accuracy............................................................................................................... 55 11.2.4 Clock Start-Up Delay.................................................................................................................. 56 11.2.5 Input Frequencies and PS Key Settings..................................................................................... 57 11.3 Crystal Oscillator (XTAL_IN, XTAL_OUT) ............................................................................................. 58 11.3.1 XTAL Mode ................................................................................................................................ 58 11.3.2 Load Capacitance ...................................................................................................................... 59 11.3.3 Frequency Trim .......................................................................................................................... 59 11.3.4 Transconductance Driver Model ................................................................................................ 60 11.3.5 Negative Resistance Model ....................................................................................................... 60 11.3.6 Crystal PS Key Settings ............................................................................................................. 60 11.3.7 Crystal Oscillator Characteristics ............................................................................................... 61 11.4 Off-Chip Program Memory..................................................................................................................... 64 11.4.1 Minimum Flash Specification ..................................................................................................... 65 11.4.2 Common Flash Interface............................................................................................................ 65 11.4.3 Memory Timing .......................................................................................................................... 66 11.5 UART Interface...................................................................................................................................... 68 11.5.1 UART Bypass............................................................................................................................. 70 11.5.2 UART Configuration While RESET is Active.............................................................................. 70 11.5.3 UART Bypass Mode................................................................................................................... 70 11.5.4 Current Consumption in UART Bypass Mode............................................................................ 70 11.6 USB Interface ........................................................................................................................................ 71
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11.6.1 USB Data Connections .............................................................................................................. 71 11.6.2 USB Pull-Up Resistor................................................................................................................. 71 11.6.3 Power Supply ............................................................................................................................. 71 11.6.4 Self Powered Mode.................................................................................................................... 72 11.6.5 Bus Powered Mode.................................................................................................................... 73 11.6.6 Suspend Current ........................................................................................................................ 74 11.6.7 Detach and Wake-Up Signalling ................................................................................................ 74 11.6.8 USB Driver ................................................................................................................................. 74 11.6.9 USB 1.1 Compliance.................................................................................................................. 75 11.6.10 USB 2.0 Compatibility........................................................................................................... 75 11.7 Serial Peripheral Interface ..................................................................................................................... 75 11.7.1 Instruction Cycle......................................................................................................................... 75 11.7.2 Writing to BlueCore4-External.................................................................................................... 76 www..com 11.7.3 Reading from BlueCore4-External ............................................................................................. 76 11.7.4 Multi Slave Operation................................................................................................................. 76 11.8 PCM Interface........................................................................................................................................ 77 11.8.1 PCM Interface Master/Slave ...................................................................................................... 78 11.8.2 Long Frame Sync....................................................................................................................... 79 11.8.3 Short Frame Sync ...................................................................................................................... 79 11.8.4 Multi Slot Operation.................................................................................................................... 80 11.8.5 GCI Interface.............................................................................................................................. 80 11.8.6 Slots and Sample Formats......................................................................................................... 81 11.8.7 Additional Features .................................................................................................................... 81 11.8.8 PCM Timing Information ............................................................................................................ 82 11.8.9 PCM Slave Timing ..................................................................................................................... 84 11.8.10 PCM_CLK and PCM_SYNC Generation .............................................................................. 86 11.8.11 PCM Configuration ............................................................................................................... 87 11.9 I/O Parallel Ports ................................................................................................................................... 88 11.9.1 PIO Defaults for BTv1.2 HCI Level Bluetooth Stack................................................................... 88 2 11.10 I C Interface ............................................................................................................................... 89 11.11 TCXO Enable OR Function........................................................................................................ 89 11.12 RESETB..................................................................................................................................... 90 11.12.1 Pin States on Reset .............................................................................................................. 90 11.12.2 Status after Reset ................................................................................................................. 91 11.13 Power Supply ............................................................................................................................. 91 11.13.1 Voltage Regulator ................................................................................................................. 91 11.13.2 Sequencing........................................................................................................................... 91 11.13.3 Sensitivity to Disturbances.................................................................................................... 91 12 Application Schematic................................................................................................................................. 92 13 Package Dimensions ................................................................................................................................... 94 13.1 8 x 8mm VFBGA 96-Ball Package......................................................................................................... 94 13.2 6 x 6mm VFBGA 96-Ball Package......................................................................................................... 95 14 Solder Profiles.............................................................................................................................................. 96 14.1 Solder Re-Flow Profile for Devices with Lead-Free Solder Balls ........................................................... 96 15 Ordering Information ................................................................................................................................... 97 15.1 BlueCore4-External ............................................................................................................................... 97 16 Tape and Reel Information .......................................................................................................................... 98 16.1 Tape Orientation and Dimensions ......................................................................................................... 98 16.2 Reel Information .................................................................................................................................. 100 16.3 Dry Pack Information ........................................................................................................................... 101 16.4 Baking Conditions................................................................................................................................ 102 16.5 Product Information ............................................................................................................................. 102 17 Contact Information................................................................................................................................... 103 18 Document References ............................................................................................................................... 104 Acronyms and Definitions................................................................................................................................ 105 Record of Changes ........................................................................................................................................... 107
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List of Figures Figure 2.1: BlueCore4-External 8 x 8mm Device Pinout (BC417143B-ES-IQN) ..................................................... 9 Figure 3.1: BlueCore4-External 6 x 6mm Device Pinout (BC417143B-ES-IRN) ................................................... 15 Figure 7.1: BlueCore4-External Device Diagram .................................................................................................. 38 Figure 9.1: BlueCore HCI Stack ............................................................................................................................ 42 Figure 9.2: BlueCore RFCOMM Stack .................................................................................................................. 46 Figure 9.3: Virtual Machine ................................................................................................................................... 48 Figure 9.4: HID Stack............................................................................................................................................ 49 Figure 11.1: Circuit TX/RX_A and TX/RX_B ......................................................................................................... 53
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Figure 11.2: Circuit RF_IN .................................................................................................................................... 54 Figure 11.3: TCXO Clock Accuracy ...................................................................................................................... 55 Figure 11.4: Actual Allowable Clock Presence Delay on XTAL_IN vs. PS Key Setting......................................... 56 Figure 11.5: Crystal Driver Circuit ......................................................................................................................... 58 Figure 11.6: Crystal Equivalent Circuit .................................................................................................................. 58 Figure 11.7: Crystal Load Capacitance and Series Resistance Limits with Crystal Frequency............................. 61 Figure 11.8: Crystal Driver Transconductance vs. Driver Level Register Setting.................................................. 62 Figure 11.9: Crystal Driver Negative Resistance as a Function of Drive Level Setting ......................................... 63 Figure 11.10: Memory Write Cycle........................................................................................................................ 66 Figure 11.11: Memory Read Cycle........................................................................................................................ 67 Figure 11.12: Universal Asynchronous Receiver .................................................................................................. 68 Figure 11.13: Break Signal.................................................................................................................................... 69 Figure 11.14: UART Bypass Architecture ............................................................................................................. 70 Figure 11.15: USB Connections for Self Powered Mode ...................................................................................... 72 Figure 11.16: USB Connections for Bus Powered Mode ...................................................................................... 73 Figure 11.17: USB_DETACH and USB_WAKE_UP Signal .................................................................................. 74 Figure 11.18: Write Operation............................................................................................................................... 76 Figure 11.19: Read Operation............................................................................................................................... 76 Figure 11.20: BlueCore4-External as PCM Interface Master ................................................................................ 78 Figure 11.21: BlueCore4-External as PCM Interface Slave .................................................................................. 78 Figure 11.22: Long Frame Sync (Shown with 8-bit Companded Sample)............................................................. 79 Figure 11.23: Short Frame Sync (Shown with 16-bit Sample) .............................................................................. 79 Figure 11.24: Multi Slot Operation with Two Slots and 8-bit Companded Samples .............................................. 80 Figure 11.25: GCI Interface................................................................................................................................... 80 Figure 11.26: 16-Bit Slot Length and Sample Formats ......................................................................................... 81 Figure 11.27: PCM Master Timing Long Frame Sync ........................................................................................... 83 Figure 11.28: PCM Master Timing Short Frame Sync........................................................................................... 83 Figure 11.29: PCM Slave Timing Long Frame Sync ............................................................................................. 85 Figure 11.30: PCM Slave Timing Short Frame Sync............................................................................................. 85 Figure 11.31: Example EEPROM Connection ...................................................................................................... 89 Figure 11.32: Example TXCO Enable OR Function .............................................................................................. 89 Figure 12.1: Application Circuit for Radio Characteristics Specification with 8 x 8mm VFBGA Package .............. 92 Figure 13.1: BlueCore4-External 96-Ball VFBGA Package Dimensions ............................................................... 94 Figure 13.2: BlueCore4-External 96-Ball VFBGA Package Dimensions ............................................................... 95 Figure 14.1: Typical Lead-Free Re-flow Solder Profile.......................................................................................... 96 Figure 16.1: Tape and Reel Orientation ................................................................................................................ 98 Figure 16.2: Tape Dimensions .............................................................................................................................. 99 Figure 16.3: Reel Dimensions ............................................................................................................................. 100
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Status Information
Figure 16.4: Tape and Reel Packaging............................................................................................................... 101 Figure 16.5: Product Information Labels ............................................................................................................. 102
List of Tables Table 10.1: Data Rate Schemes ........................................................................................................................... 51 Table 10.2: 2 bits determine phase shift between consecutive symbols ............................................................... 51 Table 10.3: /4 DQPSK......................................................................................................................................... 52 Table 10.4: 3 bits determine phase shift between consecutive symbols ............................................................... 52
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Table 11.1: External Clock Specifications ............................................................................................................. 55 Table 11.2: PS Key Values for CDMA/3G Phone TCXO Frequencies.................................................................. 57 Table 11.3: Oscillator Negative Resistance .......................................................................................................... 60 Table 11.4: Flash Device Hardware Requirements............................................................................................... 64 Table 11.5: Flash Sector Boundaries .................................................................................................................... 65 Table 11.6: Common Flash Interface Return Codes ............................................................................................. 65 Table 11.7: Possible UART Settings ..................................................................................................................... 68 Table 11.8: Standard Baud Rates ......................................................................................................................... 69 Table 11.9: USB Interface Component Values ..................................................................................................... 73 Table 11.10: Instruction Cycle for an SPI Transaction .......................................................................................... 75 Table 11.11: PCM Master Timing.......................................................................................................................... 82 Table 11.12: PCM Slave Timing............................................................................................................................ 84 Table 11.13: PSKEY_PCM_CONFIG32 Description............................................................................................. 87 Table 11.14: PSKEY_PCM_LOW_JITTER_CONFIG Description ........................................................................ 88 Table 11.15: PIO Defaults..................................................................................................................................... 88 Table 11.16: Pin States of BlueCore4-External on Reset ..................................................................................... 90 Table 16.1: Reel Dimensions .............................................................................................................................. 100 Table 16.2: Diameter Dependent Dimensions .................................................................................................... 100
_aiEceEQJbniEea~a Product Data Sheet
List of Equations Equation 11.1: Load Capacitance ......................................................................................................................... 59 Equation 11.2: Trim Capacitance .......................................................................................................................... 59 Equation 11.3: Frequency Trim ............................................................................................................................. 59 Equation 11.4: Pullability....................................................................................................................................... 59 Equation 11.5: Transconductance Required for Oscillation .................................................................................. 60 Equation 11.6: Equivalent Negative Resistance.................................................................................................... 60 Equation 11.7: Baud Rate ..................................................................................................................................... 69 Equation 11.8: PCM_CLK Frequency When Being Generated Using the Internal 48MHz clock .......................... 86 Equation 11.9: PCM_SYNC Frequency Relative to PCM_CLK ............................................................................ 86
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Status Information
Status Information
The status of this Data Sheet is Pre-Production Information. CSR Product Data Sheets progress according to the following format: Advance Information: Information for designers concerning CSR product in development. All values specified are the target values of the design. Minimum and maximum values specified are only given as guidance to the final specification limits and must not be considered as the final values. All detailed specifications including pinouts and electrical specifications may be changed by CSR without notice.
_aiEceEQJbniEea~a Product Data Sheet
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Pre-Production Information: Pinout and mechanical dimension specifications finalised. All values specified are the target values of the design. Minimum and maximum values specified are only given as guidance to the final specification limits and must not be considered as the final values. All electrical specifications may be changed by CSR without notice. Production Information: Final Data Sheet including the guaranteed minimum and maximum limits for the electrical specifications. Production Data Sheets supersede all previous document versions.
Life Support Policy and Use in Safety-Critical Applications: CSR's products are not authorised for use in life-support or safety-critical applications. Use in such applications is done at the sole discretion of the customer. CSR will not warrant the use of its devices in such applications. RoHS Compliance BlueCore4-External devices meet the requirements of Directive 2002/95/EC of the European Parliament and of the Council on the Restriction of Hazardous Substance (RoHS). Trademarks, Patents and Licenses: BlueCoreTM, BlueLabTM, CasiraTM, CompactSiraTM and MicroSiraTM are trademarks of CSR. Bluetooth(R) and the Bluetooth logos are trademarks owned by Bluetooth SIG Inc, USA and licensed to CSR. Windows(R), Windows 98TM, Windows 2000TM, Windows XPTM and Windows NTTM are registered trademarks of the Microsoft Corporation. I CTM is a trademark of Philips Corporation. All other product, service and company names are trademarks, registered trademarks or service marks of their respective owners. The publication of this information does not imply that any license is granted under any patent or other rights owned by CSR Ltd. CSR reserves the right to make technical changes to its products as part of its development programme. While every care has been taken to ensure the accuracy of the contents of this document, CSR cannot accept responsibility for any errors.
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Key Features
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Key Features
Auxiliary Features (continued)
On-chip linear regulator; 1.8V output from a 2.2 4.2V input Can run in low power mode from external 32kHz clock signal Auto baud rate setting for different TCXO frequencies Common TX/RX terminal simplifies external matching; eliminates external antenna switch BIST minimises production test time. No external trimming is required in production Full RF reference designs available Bluetooth v1.2 Specification compliant
Radio
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EDR v0.9 compliant
Power-on-reset cell detects low supply voltage Arbitrary power supply sequencing permitted 8-bit ADC available to applications
Transmitter
+6dBm RF transmit power with level control from on-chip 6-bit DAC over a dynamic range >30dB Class 2 and Class 3 support without the need for an external power amplifier or TX/RX switch Supports /4 DQPSK (2Mbps) and 8DPSK (3Mbps) modulation
Baseband and Software
External 8Mbit Flash for complete system solution Internal 48Kbyte RAM, allows full speed data transfer, mixed voice and data, and full piconet operation, including all medium rate preset types Logic for forward error correction, header error control, access code correlation, CRC, demodulation, encryption bit stream generation, whitening and transmit pulse shaping. Supports all Bluetooth v1.2 features including eSCO and AFH Transcoders for A-law, -law and linear voice from host and A-law, -law and CVSD voice over air
Receiver
Integrated channel filters Digital demodulator for improved sensitivity and co-channel rejection Real time digitised RSSI available on HCI interface Fast AGC for enhanced dynamic range Supports /4 DQPSK and 8DPSK modulation Channel classification
Physical Interfaces
Synchronous serial interface up to 4Mbaud for system debugging UART interface with programmable baud rate up to 1.5Mbaud with an optional bypass mode Full speed USB v2.0 interface supports OHCI and UHCI host interfaces Synchronous bi-directional serial programmable audio interface Optional I CTM compatible interface Optional co-existence interfaces
2
Synthesiser
Fully integrated synthesiser requires no external VCO, varactor diode, resonator or loop filter Compatible with crystals between 8 and 32MHz (in multiples of 250kHz) or an external clock Accepts 7.68, 14.44, 15.36, 16.2, 16.8, 19.2, 19.44, 19.68, 19.8 and 38.4MHz TCXO frequencies for GSM and CDMA devices with sinusoidal or logic level signals
Auxiliary Features
Crystal oscillator with built-in digital trimming Power management includes digital shut down, wake up commands with an integrated low power oscillator for ultra-low power Park/Sniff/Hold mode `Clock request' output to control an external clock
Bluetooth Stack
CSR's Bluetooth Protocol Stack runs on the on-chip MCU in a variety of configurations: Standard HCI (UART or USB) Fully embedded RFCOMM Customised builds with embedded application code
Package Options
96-ball VFBGA, 8 x 8 x 1mm, 0.65mm pitch 96-ball VFBGA, 6 x 6 x 1mm, 0.5mm pitch
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8 x 8mm VFBGA Package Information
2
2.1
8 x 8mm VFBGA Package Information
BlueCore4-External Pinout Diagram
Orientation from top of device
1
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2
3
4
5
6
7
8
9
10
11
_aiEceEQJbniEea~a Product Data Sheet
A B C D E F G H J K L
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
D1
D2
D3
D9
D10
D11
E1
E2
E3
E9
E10
E11
F1
F2
F3
F9
F10
F11
G1
G2
G3
G9
G10
G11
H1
H2
H3
H9
H10
H11
J1
J2
J3
J4
J5
J6
J7
J8
J9
J10
J11
K1
K2
K3
K4
K5
K6
K7
K8
K9
K10
K11
L1
L2
L3
L4
L5
L6
L7
L8
L9
L10
L11
Figure 2.1: BlueCore4-External 8 x 8mm Device Pinout (BC417143B-ES-IQN)
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8 x 8mm VFBGA Package Information
2.2
Radio
Device Terminal Functions (BC417143B-ES-IQN)
Ball B1 Pad Type Bi-directional with programmable strength internal pull-up/down Bi-directional with programmable strength internal pull-up/down Analogue Analogue Analogue Pad Type Analogue Analogue Pad Type CMOS output, tri-state, with weak internal pull-up CMOS input with weak internal pull-down CMOS output, tri-state, with weak internal pull-up CMOS input with weak internal pull-down Bi-directional Bi-directional Pad Type CMOS output, tri-state, with weak internal pull-down CMOS input, with weak internal pull-down Bi-directional with weak internal pull-down Bi-directional with weak internal pull-down Description Control output for external LNA (if fitted)
PIO[0]/RXEN
PIO[1]/TXEN
B2
Control output for external PA (If fitted)
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RF_IN TX_A TX_B Synthesiser and Oscillator XTAL_IN XTAL_OUT USB and UART UART_TX UART_RX UART_RTS UART_CTS USB_DP USB_DN PCM Interface PCM_OUT PCM_IN PCM_SYNC PCM_CLK
D1 F1 E1 Ball L1 L2 Ball G9 H10 H9 J11 K10 K11 Ball F9 H11 G11 G10
Single ended receiver input Transmitter output/switched receiver input Complement of TX_A Description For crystal or external clock input Drive for crystal Description UART data output UART data input UART request to send active low UART clear to send active low USB data plus with selectable internal 1.5k pull-up resistor USB data minus Description Synchronous data output Synchronous data input Synchronous data sync Synchronous data clock
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8 x 8mm VFBGA Package Information
PIO Port PIO[11]
Ball G3
Pad Type Bi-directional with programmable strength internal pull-up/down Bi-directional with programmable strength internal pull-up/down Bi-directional with programmable strength internal pull-up/down Bi-directional with programmable strength internal pull-up/down Bi-directional with programmable strength internal pull-up/down Bi-directional with programmable strength internal pull-up/down Bi-directional with programmable strength internal pull-up/down Bi-directional with programmable strength internal pull-up/down Bi-directional with programmable strength internal pull-up/down Bi-directional with programmable strength internal pull-up/down Bi-directional Bi-directional Bi-directional Pad Type CMOS input with weak internal pull-up CMOS input with weak internal pull-up CMOS input with weak internal pull-down CMOS input with weak internal pull-down CMOS output, tri-state, with weak internal pull-down CMOS input with strong internal pull-down
Description Programmable input/output line
PIO[10]
F3
Programmable input/output line
PIO[9]
E3
Programmable input/output line
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PIO[8]
D3
Programmable input/output line
PIO[7]
F10
Programmable input/output line
PIO[6]/ WLAN_Active/ Ch_Data PIO[5]/BT_Active
F11
Programmable input/output line or Optionally WLAN_Active/Ch_Data input for co-existence signalling Programmable input/output line or Optionally BT_Active output for co-existence signalling Programmable input/output line or Optionally BT_Priority/Ch_Clk output for co-existence signalling Programmable input/output line
E9
PIO[4]/ BT_Priority/Ch_Clk
E10
PIO[3]
J3
PIO[2]
H3
Programmable input/output line
AIO[0] AIO[1] AIO[2] Test and Debug RESETB SPI_CSB SPI_CLK SPI_MOSI SPI_MISO TEST_EN
K1 J2 K2 Ball B10 C11 C10 D10 C9 C8
Programmable input/output line Programmable input/output line Programmable input/output line Description Reset if low. Input debounced so must be low for >5ms to cause a reset Chip select for Synchronous Serial Interface active low Serial Peripheral Interface clock Serial Peripheral Interface data input Serial Peripheral Interface data output For test purposes only (leave unconnected)
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8 x 8mm VFBGA Package Information
External Memory Address Interface A[18] A[17] A[16] A[15] A[14] A[13] A[12]
www..com A[11]
Ball L7 K7 A10 L10 K9 J9 L9 J8 K8 L8 J7 J5 L6 K6 K5 L5 J4 K4 A3
Pad Type CMOS output, tri-state CMOS output, tri-state CMOS output, tri-state CMOS output, tri-state CMOS output, tri-state CMOS output, tri-state CMOS output, tri-state CMOS output, tri-state CMOS output, tri-state CMOS output, tri-state CMOS output, tri-state CMOS output, tri-state CMOS output, tri-state CMOS output, tri-state CMOS output, tri-state CMOS output, tri-state CMOS output, tri-state CMOS output, tri-state CMOS output, tri-state
Description Address line Address line Address line Address line Address line Address line Address line
_aiEceEQJbniEea~a Product Data Sheet
Address line Address line Address line Address line Address line Address line Address line Address line Address line Address line Address line Address line
A[10] A[9] A[8] A[7] A[6] A[5] A[4] A[3] A[2] A[1] A[0]
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8 x 8mm VFBGA Package Information
External Memory Data Interface D[15] D[14] D[13] D[12] D[11] www..com D[10] D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
Ball B9 B8 C7 A7 B6 C5 A5 B4 A9 A8 B7 C6 A6 B5 C4 A4
Pad Type Bi-directional with weak internal pull-down Bi-directional with weak internal pull-down Bi-directional with weak internal pull-down Bi-directional with weak internal pull-down Bi-directional with weak internal pull-down Bi-directional with weak internal pull-down Bi-directional with weak internal pull-down Bi-directional with weak internal pull-down Bi-directional with weak internal pull-down Bi-directional with weak internal pull-down Bi-directional with weak internal pull-down Bi-directional with weak internal pull-down Bi-directional with weak internal pull-down Bi-directional with weak internal pull-down Bi-directional with weak internal pull-down Bi-directional with weak internal pull-down Pad Type CMOS output, tri-state with internal weak pull-up CMOS output, tri-state with internal weak pull-up CMOS output, tri-state with internal weak pull-up
Description Data line Data line Data line Data line Data line Data line Data line Data line Data line Data line Data line Data line Data line Data line Data line Data line
_aiEceEQJbniEea~a Product Data Sheet
External Memory Interface REB WEB CSB
Ball C3 J6 B3
Description Read enable for external memory (active low) Write enable for external memory (active low) Chip select for external memory (active low)
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8 x 8mm VFBGA Package Information
Power Supplies and Control VREG_IN VREG_EN VDD_USB VDD_PIO VDD_PADS VDD_MEM VDD_CORE VDD_RADIO VDD_LO VDD_ANA
Ball L4 H2 L11 A2 D11 A11 E11 C1 J1 G2, L3
Pad Type VDD/Regulator input CMOS input VDD VDD VDD VDD VDD VDD VDD VDD/Regulator output
Description Linear regulator input High or not connected to enable regulator. VSS to disable regulator Positive supply for UART/USB ports Positive supply for PIO
(1)
Positive supply for all other digital (2) Input/Output ports Positive supply for external memory and AIO ports Positive supply for internal digital circuitry Positive supply for RF circuitry Positive supply for VCO and synthesiser circuitry Positive supply for analogue circuitry and 1.8V regulated output. For performance, regulator decoupling and loads should be connected to ball adjacent to VREG_IN Ground connection for digital ports
_aiEceEQJbniEea~a Product Data Sheet
www..com
VSS_DIG
A1, D9, J10 D2, E2, F2 H1 G1, K3
VSS
VSS_RADIO
VSS
Ground connections for RF circuitry
VSS_LO VSS_ANA
Notes:
(1) (2)
VSS VSS
Ground connections for VCO and synthesiser Ground connections for analogue circuitry
Positive supply for PIO[3:0] and PIO[11:8] Positive supply for SPI/PCM ports and PIO[7:4] Ball B11, C2 Description Leave unconnected
Unconnected Terminals
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6 x 6mm VFBGA Package Information
3
3.1
6 x 6mm VFBGA Package Information
BlueCore4-External 6 x 6mm Pinout Diagram
Orientation from top of device
1
www..com
2
3
4
5
6
7
8
9
10
11
_aiEceEQJbniEea~a Product Data Sheet
A B C D E F G H J K L
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
D1
D2
D3
D9
D10
D11
E1
E2
E3
E9
E10
E11
F1
F2
F3
F9
F10
F11
G1
G2
G3
G9
G10
G11
H1
H2
H3
H9
H10
H11
J1
J2
J3
J4
J5
J6
J7
J8
J9
J10
J11
K1
K2
K3
K4
K5
K6
K7
K8
K9
K10
K11
L1
L2
L3
L4
L5
L6
L7
L8
L9
L10
L11
Figure 3.1: BlueCore4-External 6 x 6mm Device Pinout (BC417143B-ES-IRN)
BC417143B-ds-001Pc
(c) Copyright Cambridge Silicon Radio Limited 2004 Pre-Production Information
Page 15 of 107
6 x 6mm VFBGA Package Information
3.2
Radio
Device Terminal Functions (BC417143B-ES-IRN)
Ball C1 Pad Type Bi-directional with programmable strength internal pull-up/down Bi-directional with programmable strength internal pull-up/down Analogue Analogue Analogue Pad Type Analogue Analogue Pad Type CMOS output, tri-state, with weak internal pull-up CMOS input with weak internal pull-down CMOS output, tri-state, with weak internal pull-up CMOS input with weak internal pull-down Bi-directional Bi-directional Pad Type CMOS output, tri-state, with weak internal pull-down CMOS input, with weak internal pull-down Bi-directional with weak internal pull-down Bi-directional with weak internal pull-down Description Control output for external LNA (if fitted)
PIO[0]/RXEN
PIO[1]/TXEN
C2
Control output for external PA (If fitted)
www..com
RF_IN TX_A TX_B Synthesiser and Oscillator XTAL_IN XTAL_OUT USB and UART UART_TX UART_RX UART_RTS UART_CTS USB_DP USB_DN PCM Interface PCM_OUT PCM_IN PCM_SYNC PCM_CLK
D1 F1 E1 Ball L1 L2 Ball G9 H10 H9 J11 K10 K11 Ball F9 H11 G11 G10
Single ended receiver input Transmitter output/switched receiver input Complement of TX_A Description For crystal or external clock input Drive for crystal Description UART data output UART data input UART request to send active low UART clear to send active low USB data plus with selectable internal 1.5k pull-up resistor USB data minus Description Synchronous data output Synchronous data input Synchronous data sync Synchronous data clock
_aiEceEQJbniEea~a Product Data Sheet
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6 x 6mm VFBGA Package Information
PIO Port PIO[11]
Ball D2
Pad Type Bi-directional with programmable strength internal pull-up/down Bi-directional with programmable strength internal pull-up/down Bi-directional with programmable strength internal pull-up/down Bi-directional with programmable strength internal pull-up/down Bi-directional with programmable strength internal pull-up/down Bi-directional with programmable strength internal pull-up/down Bi-directional with programmable strength internal pull-up/down Bi-directional with programmable strength internal pull-up/down Bi-directional with programmable strength internal pull-up/down Bi-directional with programmable strength internal pull-up/down Bi-directional Bi-directional Bi-directional Pad Type CMOS input with weak internal pull-up CMOS input with weak internal pull-up CMOS input with weak internal pull-down CMOS input with weak internal pull-down CMOS output, tri-state, with weak internal pull-down CMOS input with strong internal pull-down
Description Programmable input/output line
PIO[10]
F3
Programmable input/output line
PIO[9]
G3
Programmable input/output line
_aiEceEQJbniEea~a Product Data Sheet
www..com
PIO[8]
H3
Programmable input/output line
PIO[7]
F10
Programmable input/output line
PIO[6]/ WLAN_Active/ Ch_Data PIO[5]/BT_Active
F11
Programmable input/output line or Optionally WLAN_Active/Ch_Data input for co-existence signalling Programmable input/output line or Optionally BT_Active output for co-existence signalling Programmable input/output line or Optionally BT_Priority/Ch_Clk output for co-existence signalling Programmable input/output line
E9
PIO[4]/ BT_Priority/Ch_Clk
E10
PIO[3]
B2
PIO[2]
J3
Programmable input/output line
AIO[0] AIO[1] AIO[2] Test and Debug RESETB SPI_CSB SPI_CLK SPI_MOSI SPI_MISO TEST_EN
L4 K3 K2 Ball D10 C11 B9 C10 C9 C8
Programmable input/output line Programmable input/output line Programmable input/output line Description Reset if low. Input debounced so must be low for >5ms to cause a reset Chip select for Synchronous Serial Interface active low Serial Peripheral Interface clock Serial Peripheral Interface data input Serial Peripheral Interface data output For test purposes only (leave unconnected)
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6 x 6mm VFBGA Package Information
External Memory Address Interface A[18] A[17] A[16] A[15] A[14] A[13] A[12]
www..com A[11]
Ball L7 K7 A9 L10 K9 J9 L9 J8 K8 L8 J7 K6 L6 K5 J5 L5 J4 K4 A2
Pad Type CMOS output, tri-state CMOS output, tri-state CMOS output, tri-state CMOS output, tri-state CMOS output, tri-state CMOS output, tri-state CMOS output, tri-state CMOS output, tri-state CMOS output, tri-state CMOS output, tri-state CMOS output, tri-state CMOS output, tri-state CMOS output, tri-state CMOS output, tri-state CMOS output, tri-state CMOS output, tri-state CMOS output, tri-state CMOS output, tri-state CMOS output, tri-state
Description Address line Address line Address line Address line Address line Address line Address line
_aiEceEQJbniEea~a Product Data Sheet
Address line Address line Address line Address line Address line Address line Address line Address line Address line Address line Address line Address line
A[10] A[9] A[8] A[7] A[6] A[5] A[4] A[3] A[2] A[1] A[0]
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6 x 6mm VFBGA Package Information
External Memory Data Interface D[15] D[14] D[13] D[12] D[11] www..com D[10] D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
Ball B8 B7 C7 A6 B5 C5 A4 B3 A8 A7 B6 C6 A5 B4 C4 A3
Pad Type Bi-directional with weak internal pull-down Bi-directional with weak internal pull-down Bi-directional with weak internal pull-down Bi-directional with weak internal pull-down Bi-directional with weak internal pull-down Bi-directional with weak internal pull-down Bi-directional with weak internal pull-down Bi-directional with weak internal pull-down Bi-directional with weak internal pull-down Bi-directional with weak internal pull-down Bi-directional with weak internal pull-down Bi-directional with weak internal pull-down Bi-directional with weak internal pull-down Bi-directional with weak internal pull-down Bi-directional with weak internal pull-down Bi-directional with weak internal pull-down Pad Type CMOS output, tri-state with internal weak pull-up CMOS output, tri-state with internal weak pull-up CMOS output, tri-state with internal weak pull-up
Description Data line Data line Data line Data line Data line Data line Data line Data line Data line Data line Data line Data line Data line Data line Data line Data line
_aiEceEQJbniEea~a Product Data Sheet
External Memory Interface REB WEB CSB
Ball C3 J6 D3
Description Read enable for external memory (active low) Write enable for external memory (active low) Chip select for external memory (active low)
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6 x 6mm VFBGA Package Information
Power Supplies and Control VREG_IN VREG_EN VDD_USB VDD_PIO VDD_PADS VDD_MEM VDD_CORE VDD_RADIO VDD_LO VDD_ANA
Ball K1 H2 L11 A1 D11 B10 E11 G1 J1 L3
Pad Type VDD/Regulator input CMOS input VDD VDD VDD VDD VDD VDD VDD VDD/Regulator output
Description Linear regulator input High or not connected to enable regulator. VSS to disable regulator Positive supply for UART/USB ports Positive supply for PIO
(1)
Positive supply for all other digital (2) Input/Output ports Positive supply for external memory and AIO ports Positive supply for internal digital circuitry Positive supply for RF circuitry Positive supply for VCO and synthesiser circuitry Positive supply for analogue circuitry and 1.8V regulated output. For performance, regulator decoupling and loads should be connected to ball adjacent to VREG_IN Ground connection for digital ports
_aiEceEQJbniEea~a Product Data Sheet
www..com
VSS_DIG
B1, D9, J10 E2, F2, G2 H1 J2
VSS
VSS_RADIO
VSS
Ground connections for RF circuitry
VSS_LO VSS_ANA
Notes:
(1) (2)
VSS VSS
Ground connections for VCO and synthesiser Ground connections for analogue circuitry
Positive supply for PIO[3:0] and PIO[11:8] Positive supply for SPI/PCM ports and PIO[7:4]
Unconnected Terminals
Ball A10, A11, B11, E3
Description Leave unconnected
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Electrical Characteristics
4
Electrical Characteristics
Min -40C -0.4V -0.4V -0.4V VSS-0.4V Max +150C 2.2V 3.7V 5.6V VDD+0.4V
Absolute Maximum Ratings Rating Storage Temperature Supply Voltage: VDD_RADIO, VDD_LO, VDD_ANA and VDD_CORE Supply Voltage: VDD_MEM, VDD_PADS, VDD_PIO and www..com VDD_USB Supply Voltage: VREG_IN Other Terminal Voltages Recommended Operating Conditions Operating Condition Operating Temperature Range Guaranteed RF performance range
(1)
_aiEceEQJbniEea~a Product Data Sheet
Min -40C -40C 1.7V 1.7V 2.2V
Max +105C +105C 1.9V 3.6V 4.2V
(1)
Supply Voltage: VDD_RADIO, VDD_LO, VDD_ANA and VDD_CORE Supply Voltage: VDD_MEM, VDD_PADS, VDD_PIO and VDD_USB Supply Voltage: VREG_IN
Note:
(1)
The device will operate without damage with VREG_IN as high as 5.6V, however the RF performance is not guaranteed above 4.2V
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Electrical Characteristics
Input/Output Terminal Characteristics Linear Regulator Normal Operation Output Voltage (Iload = 70 mA) Temperature Coefficient Output Noise
(1)(2)
Min
Typ
Max
Unit
1.70 -250 140 5 25
1.78 35
1.85 +250 1 50 50 4.2
(6)
V ppm/C mV rms mV/A s mA A V mV A
Load Regulation (Iload < 100 mA)
www..com
Settling Time
(1)(3)
_aiEceEQJbniEea~a Product Data Sheet
Maximum Output Current Minimum Load Current Input Voltage Dropout Voltage (Iload = 70 mA) Quiescent Current (excluding Ioad, Iload < 1mA) Low Power Mode
(4)
350 50
Quiescent Current (excluding Ioad, Iload < 100A) Disabled Mode
(5)
4
7
10
A
Quiescent Current
Notes:
1.5
2.5
3.5
A
For optimum performance the VDD_ANA ball adjacent to VREG_IN should be used for regulator output
(1) (2) (3) (4) (5) (6)
Regulator output connected to 47nF pure and 4.7F 2.2 ESR capacitors. Frequency range 100Hz to 100kHz 1mA to 70mA pulsed load Low power mode is entered and exited automatically when the chip enters/leaves Deep Sleep mode. Regulator is disabled when VREG_IN is either open circuit or driven to the same voltage as VDD_ANA Operation up to 5.6V is permissible without damage and without the output voltage rising sufficiently to damage the rest of BlueCore4, but output regulation and other specifications are no longer guaranteed at input voltages in excess of 4.2V.
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Electrical Characteristics
Input/Output Terminal Characteristics (Continued) Digital Terminals Input Voltage Levels VIL input logic level low VIH input logic level high Output Voltage Levels VOL output logic level low, (lo www..com = 4.0mA), 2.7V VDD 3.0V VOL output logic level low, (lo = 4.0mA), 1.7V VDD 1.9V VOH output logic level high, (lo = -4.0mA), 2.7V VDD 3.0V VOH output logic level high, (lo = -4.0mA), 1.7V VDD 1.9V Input and Tri-state Current with: Strong pull-up Strong pull-down Weak pull-up Weak pull-down I/O pad leakage current CI Input Capacitance Input/Output Terminal Characteristics (Continued) USB Terminals VDD_USB for correct USB operation Input threshold VIL input logic level low VIH input logic level high Input leakage current VSS_PADS < VIN < VDD_USB CI Input capacitance Output Voltage levels To correctly terminated USB Cable VOL output logic level low VOH output logic level high Input/Output Terminal Characteristics (Continued) Power-on reset VDD_CORE falling threshold VDD_CORE rising threshold Hysteresis Min 1.40 1.50 0.05 Typ 1.50 1.60 0.10 Max 1.60 1.70 0.15 Unit V V V 0.0 2.8 0.2 VDD_USB V V
(1)
Min
Typ
Max
Unit
2.7V VDD 3.0V 1.7V VDD 1.9V
-0.4 -0.4 0.7VDD
-
+0.8 +0.4 VDD+0.4
V V V
VDD-0.2 VDD-0.4
-
0.2 0.4 -
V V V V
_aiEceEQJbniEea~a Product Data Sheet
-100 +10 -5.0 +0.2 -1 1.0
-40 +40 -1.0 +1.0 0 -
-10 +100 -0.2 +5.0 +1 5.0
A A A A A pF
Min 3.1 0.7VDD_USB -1 2.5
Typ
Max 3.6
Unit V V V A pF
1 -
0.3VDD_USB 5 10.0
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Electrical Characteristics
Input/Output Terminal Characteristics (Continued) Auxiliary ADC Resolution Input voltage range (LSB size = VDD_ANA/255) Accuracy (Guaranteed monotonic) Offset Gain Error www..com Input Bandwidth Conversion time Sample rate
(2)
Min 0 INL DNL -1 0 -1 -0.8 -
Typ 100 2.5 -
Max 8 VDD_ANA 1 1 1 0.8 700
Unit Bits V LSB LSB LSB % kHz s Samples/s
_aiEceEQJbniEea~a Product Data Sheet
Input/Output Terminal Characteristics (Continued) Crystal Oscillator Crystal frequency Digital trim range Trim step size
(5) (4) (5)
Min 8.0 5.0 2.0
(6)
Typ 6.2 0.1 1500
Max 32.0 8.0 2400
Unit MHz pF pF mS
Transconductance Negative resistance External Clock Input frequency Allowable Jitter XTAL_IN input impedance XTAL_IN input capacitance
Notes:
(7) (8)
870
7.5 0.2 -
7
40.0 VDD_ANA 15 -
MHz V pk-pk ps rms k pF
Clock input level
VDD_CORE, VDD_RADIO, VDD_LO and VDD_ANA are at 1.8V unless shown otherwise VDD_PADS, VDD_PIO and VDD_USB are at 3.0V unless shown otherwise The same setting of the digital trim is applied to both XTAL_IN and XTAL_OUT. Current drawn into a pin is defined as positive; current supplied out of a pin is defined as negative.
(1) (2)
Internal USB pull-up disabled Access of ADC is through VM function and therefore sample rate given is achieved as part of this function Specified for an output voltage between 0.2V and VDD_PIO -0.2V Integer multiple of 250kHz The difference between the internal capacitance at minimum and maximum settings of the internal digital trim XTAL frequency = 16MHz; XTAL C0 = 0.75pF; XTAL load capacitance = 8.5pF Clock input can be any frequency between 8 and 40MHz in steps of 250kHz and also covers the CDMA/3G TCXO frequencies of 7.68, 14.44, 15.36, 16.2, 16.8, 19.2, 19.44, 19.68, 19.8 and 38.4MHz Clock input can either be sinusoidal or square wave. If the peaks of the signal are below VSS_ANA or above VDD_ANA a DC blocking capacitor is required between the signal and XTAL_IN
(3) (4) (5)
(6) (7)
(8)
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Radio Characteristics - Basic Data Rate
5
5.1 5.1.1
Radio Characteristics - Basic Data Rate
Temperature +20C Transmitter
VDD = 1.8V Temperature = +20C Min Typ 6.5 35 0.5 820 -35 -45 165 140 0.9 10 8 9 10 Typ -143 -138 -131 -135 -135 -137 -132 -135 Max 1000 -20 -40 175 35 20 20 25 Max -138 -135 -115 -125 -126 -130 -122 -127 Bluetooth Specification -6 to +4 16 1000 -20 -40 140(4)
Radio Characteristics
Unit dBm dB dB kHz dBm dBm kHz kHz kHz kHz/ 50s kHz kHz Unit dBMHz dBMHz dBMHz dBMHz dBMHz dBMHz dBMHz dBMHz
Maximum RF transmit power www..com RF power control range
(1)(2)
(1)(2)(3)
3 25 (5) (5)
_aiEceEQJbniEea~a Product Data Sheet
RF power range control resolution 20dB bandwidth for modulated carrier Adjacent channel transmit power F=F0 2MHz f1avg "Maximum Modulation" f2max "Minimum Modulation" f1avg/f2avg Initial carrier frequency tolerance Drift Rate Drift (single slot packet) Drift (five slot packet) Emissions Emitted power in cellular bands measured at chip terminals Output power 4dBm Frequency (GHz) 0.925-0.960 1.570-1.580 1.805-1.880 1.930-1.990 1.930-1.990 1.930-1.990 2.110-2.170 2.110-2.170
Notes:
140 115 0.8 Min -
Adjacent channel transmit power F=F0 3MHz
Results shown are referenced to input of the RF balun
(1) (2) (3) (4) (5)
Power at the chip pads Measured according to the Bluetooth specification v1.2 The firmware maintains the transmit power to be within the Bluetooth specification v1.2 limits Class 2 RF transmit power range, Bluetooth specification v1.2 Measured at F0 = 2441MHz
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Radio Characteristics - Basic Data Rate
5.1.2
Receiver
VDD = 1.8V Temperature = +20C Min 0 (1)(2)
Radio Characteristics
Frequency (GHz) Sensitivity at 0.1% BER for all packet types 2.402 2.441 2.480
Typ -84 -85 -85 3 9 -4 -4 -35 -21 -45 -45 -18 -30 -140 Typ 2 7 6 5 -6 -5 -4 -3 -4 -14
Max -80 -81 -81 11 0 0 -30 -20 -9 -39 Max -
Bluetooth Specification
Unit dBm
-70 -20 11 0 0 -30 -20 -40 -40 -9 -39 Modulation GSM GSM GSM GSM W_CDMA GSM GSM GSM GSM W_CDMA
dBm dBm dBm dB dB dB dB dB dB dB dB dBm dBm/Hz Unit dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm
Maximum received signal at 0.1% BER
www..comco-channel C/I
_aiEceEQJbniEea~a Product Data Sheet
Adjacent channel selectivity C/I F=F0 +1MHz Adjacent channel selectivity C/I F=F0 -1MHz Adjacent channel selectivity C/I F=F0 -2MHz
-
(1)(2) (1)(2)
Adjacent channel selectivity C/I F=F0 +2MHz Adjacent channel selectivity C/I FF0 +3MHz Adjacent channel selectivity C/I FF0 -5MHz Adjacent channel selectivity C/I F=FImage Spurious output level Blocking Continuous power in cellular bands required to block Bluetooth reception (for Bluetooth sensitivity of -67dBm with 0.1% BER) Measured at chip terminals Continuous power in cellular bands required to block Bluetooth reception (for sensitivity of -80dBm with 0.1% BER) measured at chip terminals
Notes:
(4) (1)(2)
(1)(2) (1)(2) (1)(2)
Maximum level of intermodulation interferers
(3)
Frequency (GHz) 0.824-0.849
(5)
Min -2 5 3 1 -8 -10 -8 -7 -11 -18
0.880-0.915 1.710-1.785 1.850-1.910 1.920-1.980 0.824-0.849
(5)
0.880-0.915 1.710-1.785 1.850-1.910 1.920-1.980
Results shown are referenced to input of the RF balun
(1)
Up to five exceptions are allowed in v1.2 of the Bluetooth specification. BlueCore4-External is guaranteed to meet the C/I performance as specified by the Bluetooth specification v1.2. Measured at F0 = 2405MHz, 2441MHz, 2477MHz Measured at f1-f2 = 5MHz. Measurement is performed in accordance with Bluetooth RF test RCV/CA/05/c. i.e. wanted signal at -64dBm Integrated in 100kHz bandwidth. Actual figure is typically below -140dBm/Hz except for peaks of -125dBm/Hz at 1.2GHz and -100dBm/Hz in-band at 2.4GHz | 3fBlocking - fBluetooth | > 4MHz
(2) (3)
(4)
(5)
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Radio Characteristics - Basic Data Rate
5.2 5.2.1
Temperature -40C Transmitter
VDD = 1.8V Temperature = -40C Min Typ 8 35 0.5 820 -35 -45 165 135 0.9 10 8 9 10 Max 1000 -20 -40 175 35 25 25 40 Bluetooth Specification -6 to +4 16 1000 -20 -40 140(2)
Radio Characteristics
Unit dBm dB
Maximum RF transmit power RF power control range
(1)
4 25 (3) (4) (3) (4)
_aiEceEQJbniEea~a Product Data Sheet
www..com power range control resolution RF
dB kHz dBm dBm kHz kHz kHz kHz/50s kHz kHz
20dB bandwidth for modulated carrier Adjacent channel transmit power F=F0 2MHz Adjacent channel transmit power F=F0 3MHz f1avg "Maximum Modulation" f2max "Minimum Modulation" f2avg / f1avg Initial carrier frequency tolerance Drift Rate Drift (single slot packet) Drift (five slot packet)
Notes:
(1)
140 115 0.8 -
BlueCore4-External firmware maintains the transmit power to be within the Bluetooth specification v1.2 limits Class 2 RF transmit power range, Bluetooth specification v1.2 Measured at F0 = 2441MHz Up to three exceptions are allowed in v1.2 of the Bluetooth specification
(2) (3) (4)
5.2.2
Receiver
VDD = 1.8V Temperature = -40C Frequency (GHz) Min -2 Typ -86.0 -88.0 -86.5 1 Max -81 -82 -82 -20 dBm -70 dBm Bluetooth Specification Unit
Radio Characteristics
Sensitivity at 0.1% BER for all packet types Maximum received signal at 0.1% BER
2.402 2.441 2.480
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Radio Characteristics - Basic Data Rate
5.3 5.3.1
Temperature -25C Transmitter
VDD = 1.8V Temperature = -25C Min Typ 7 35 0.5 820 -35 -45 165 140 0.9 10 8 9 10 Max 1000 -20 -40 175 35 20 20 25 Bluetooth Specification -6 to +4 16 1000 -20 -40 140(2)
Radio Characteristics
Unit dBm dB
Maximum RF transmit power RF power control range
(1)
3.5 25 (3) (4) (3) (4)
_aiEceEQJbniEea~a Product Data Sheet
www..com power range control resolution RF
dB kHz dBm dBm kHz kHz kHz kHz/50s kHz kHz
20dB bandwidth for modulated carrier Adjacent channel transmit power F=F0 2MHz Adjacent channel transmit power F=F0 3MHz f1avg "Maximum Modulation" f2max "Minimum Modulation" f2avg / f1avg Initial carrier frequency tolerance Drift Rate Drift (single slot packet) Drift (five slot packet)
Notes:
(1)
140 115 0.8 -
BlueCore4-External firmware maintains the transmit power to be within the Bluetooth specification v1.2 limits Class 2 RF transmit power range, Bluetooth specification v1.2 Measured at F0 = 2441MHz Up to three exceptions are allowed in v1.2 of the Bluetooth specification
(2) (3) (4)
5.3.2
Receiver
VDD = 1.8V Temperature = -25C Frequency (GHz) Min -2 Typ -85.5 -86.5 -86.5 1 Max -81 -82 -82 -20 dBm -70 dBm Bluetooth Specification Unit
Radio Characteristics
Sensitivity at 0.1% BER for all packet types Maximum received signal at 0.1% BER
2.402 2.441 2.480
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Radio Characteristics - Basic Data Rate
5.4 5.4.1
Temperature +85C Transmitter
VDD = 1.8V Temperature = +85C Min Typ 3 35 0.5 820 -35 -45 165 140 0.9 10 9 9 10 Max 1000 -20 -40 175 35 20 20 28 Bluetooth Specification -6 to +4 16 1000 -20 -40 140(2)
Radio Characteristics
Unit dBm dB
Maximum RF transmit power RF power control range
(1)
0 25 (3) (4) (3) (4)
_aiEceEQJbniEea~a Product Data Sheet
www..com power range control resolution RF
dB kHz dBm dBm kHz kHz kHz kHz/50s kHz kHz
20dB bandwidth for modulated carrier Adjacent channel transmit power F=F0 2MHz Adjacent channel transmit power F=F0 3MHz f1avg "Maximum Modulation" f2max "Minimum Modulation" f2avg / f1avg Initial carrier frequency tolerance Drift Rate Drift (single slot packet) Drift (five slot packet)
Notes:
(1)
140 115 0.8 -
BlueCore4-External firmware maintains the transmit power to be within the Bluetooth specification v1.2 limits Class 2 RF transmit power range, Bluetooth specification v1.2 Measured at F0 = 2441MHz Up to three exceptions are allowed in v1.2 of the Bluetooth specification
(2) (3) (4)
5.4.2
Receiver
VDD = 1.8V Temperature = +85C Frequency (GHz) Min 0 Typ -81 -83 -83 5 Max -77 -79 -79 -20 dBm -70 dBm Bluetooth Specification Unit
Radio Characteristics
Sensitivity at 0.1% BER for all packet types Maximum received signal at 0.1% BER
2.402 2.441 2.480
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Radio Characteristics - Basic Data Rate
5.5 5.5.1
Temperature +105C Transmitter
VDD = 1.8V Temperature = +105C Min Typ 1 35 0.5 820 -35 -45 165 135 0.9 10 9 9 10 Max 1000 -20 -40 175 35 25 25 40 Bluetooth Specification -6 to +4 16 1000 -20 -40 140(2)
Radio Characteristics
Unit dBm dB
Maximum RF transmit power RF power control range
(1)
-2.5 25 (3) (4) (3) (4)
_aiEceEQJbniEea~a Product Data Sheet
www..com power range control resolution RF
dB kHz dBm dBm kHz kHz kHz kHz/50s kHz kHz
20dB bandwidth for modulated carrier Adjacent channel transmit power F=F0 2MHz Adjacent channel transmit power F=F0 3MHz f1avg "Maximum Modulation" f2max "Minimum Modulation" f2avg / f1avg Initial carrier frequency tolerance Drift Rate Drift (single slot packet) Drift (five slot packet)
Notes:
(1)
140 -
BlueCore4-External firmware maintains the transmit power to be within the Bluetooth specification v1.2 limits Class 2 RF transmit power range, Bluetooth specification v1.2 Measured at F0 = 2441MHz Up to three exceptions are allowed in v1.2 of the Bluetooth specification
(2) (3) (4)
5.5.2
Receiver
VDD = 1.8V Temperature = +105C Frequency (GHz) Min 0 Typ -81 -82 -82 5 Max -77 -78 -78 -20 dBm -70 dBm Bluetooth Specification Unit
Radio Characteristics
Sensitivity at 0.1% BER for all packet types Maximum received signal at 0.1% BER
2.402 2.441 2.480
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Radio Characteristics - Basic Data Rate
5.6
Power Consumption
Typical Average Current Consumption VDD=1.8V Mode SCO connection HV3 (30ms interval Sniff Mode) (Slave) SCO connection HV3 (30ms interval Sniff Mode) (Master) SCO connection HV3 (No Sniff Mode) (Slave)
www..com SCO connection HV1 (Slave)
Temperature = +20C
Output Power = +4dBm Average 21 21 28 42 42 5 22 45 45 3.2 0.45 0.55 47.0 15.0 Unit mA mA mA
_aiEceEQJbniEea~a Product Data Sheet
mA mA mA mA mA mA mA mA mA A A
SCO connection HV1 (Master) ACL data transfer 115.2kbps UART no traffic (Master) ACL data transfer 115.2kbps UART no traffic (Slave) ACL data transfer 720kbps UART (Master or Slave) ACL data transfer 720kbps USB (Master or Slave) ACL connection, Sniff Mode 40ms interval, 38.4kbps UART ACL connection, Sniff Mode 1.28s interval, 38.4kbps UART Parked Slave, 1.28s beacon interval, 38.4kbps UART Standby Mode (Connected to host, no RF activity) Reset (RESETB low)
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Radio Characteristics - Enhanced Data Rate
6
6.1 6.1.1
Radio Characteristics - Enhanced Data Rate
Temperature +20C Transmitter
VDD = 1.8V Min Typ 6 -1
(3)
Radio Characteristics
Temperature = +20C Max Bluetooth Specification -6 to +4 10 13 20 25
(5) (5) (5) (2)
Unit
_aiEceEQJbniEea~a Product Data Sheet
www..com
Maximum RF transmit power Relative transmit power
(3)
(1)
dBm dB kHz % % %
-4 to +1
Carrier frequency stability Modulation Accuracy
(3)(4)
3 RMS DEVM 99% DEVM Peak DEVM 10 15 20
Notes:
Results shown are referenced to input of the RF balun
(1)
BlueCore4-External firmware maintains the transmit power to be within the Bluetooth specification v1.2 limits Class 2 RF transmit power range, Bluetooth specification v1.2 Measurements methods are in accordance with the EDR RF Test Specification v0.9 Modulation accuracy utilises differential error vector magnitude (DEVM) with tracking of the carrier frequency drift. The Bluetooth specification values are for 8DPSK modulation (values for the /4 DQPSK modulation are less stringent)
(2) (3) (4)
(5)
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Radio Characteristics - Enhanced Data Rate
6.1.2
Receiver
VDD = 1.8V Temperature = +20C Min Typ -86 -79 -6 -7 +11 +19 -8 -2 -8 -2 -35 -35 -23 -19 -43 -40 -43 -38 -17 -10 Max Bluetooth Specification -70 -70 -20 -20 +13 +21 0 +5 0 +5 -30 -25 -20 -13 -40 -33 -40 -33 -7 0 Unit dBm dBm dBm dBm dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB
Radio Characteristics
Modulation Sensitivity at 0.01% BER
(1)
/4 DQPSK 8DPSK /4 DQPSK 8DPSK
(1)
Maximum received signal at (1) 0.1% BER
www..com
_aiEceEQJbniEea~a Product Data Sheet
C/I co-channel at 0.1% BER Adjacent channel selectivity (1)(2)(3) C/I F=F0 +1MHz Adjacent channel selectivity (1)(2)(3) C/I F=F0 -1MHz Adjacent channel selectivity (1)(2)(3) C/I F=F0 +2MHz Adjacent channel selectivity (1)(2)(3) C/I F=F0 -2MHz Adjacent channel selectivity (1)(2)(3) C/I FF0 +3MHz Adjacent channel selectivity (1)(2)(3) C/I FF0 -5MHz Adjacent channel selectivity (1)(2)(3) C/I F=FImage
Notes:
/4 DQPSK 8DPSK /4 DQPSK 8DPSK /4 DQPSK 8DPSK /4 DQPSK 8DPSK /4 DQPSK 8DPSK /4 DQPSK 8DPSK /4 DQPSK 8DPSK /4 DQPSK 8DPSK
Results shown are referenced to input of the RF balun
(1) (2)
Measurements methods are in accordance with the EDR RF Test Specification v0.9 Up to five exceptions are allowed in EDR RF Test Specification v0.9. BlueCore4-External is guaranteed to meet the C/I performance as specified by the EDR RF Test Specification v0.9. Measured at F0 = 2405MHz, 2441MHz, 2477MHz
(3)
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Radio Characteristics - Enhanced Data Rate
6.2 6.2.1
Temperature -40C Transmitter
VDD = 1.8V Min Typ 8 -1 3 RMS DEVM 10 15 20 99% DEVM Peak DEVM Temperature = -40C Max Bluetooth Specification -6 to +4 10 13 20 25
(5) (5) (5) (2)
Radio Characteristics
Unit dBm dB
Maximum RF transmit power Relative transmit power
(3) (3) www..com Carrier frequency stability
(1)
-4 to +1
_aiEceEQJbniEea~a Product Data Sheet
kHz % % %
Modulation Accuracy
(3)(4)
Notes:
Results shown are referenced to input of the RF balun
(1)
BlueCore4-External firmware maintains the transmit power to be within the Bluetooth specification v1.2 limits Class 2 RF transmit power range, Bluetooth specification v1.2 Measurements methods are in accordance with the EDR RF Test Specification v0.9 Modulation accuracy utilises differential error vector magnitude (DEVM) with tracking of the carrier frequency drift. The Bluetooth specification values are for 8DPSK modulation (values for the /4 DQPSK modulation are less stringent)
(2) (3) (4)
(5)
6.2.2
Receiver
VDD = 1.8V Temperature = -40C Min Typ -89 -82 -10 -10 Max Bluetooth Specification -70 -70 -20 -20 Unit dBm dBm dBm dBm
Radio Characteristics
Modulation Sensitivity at 0.01% BER
(1)
/4 DQPSK 8DPSK /4 DQPSK 8DPSK
Maximum received signal at (1) 0.1% BER
Notes:
Results shown are referenced to input of the RF balun
(1)
Measurements methods are in accordance with the EDR RF Test Specification v0.9
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Radio Characteristics - Enhanced Data Rate
6.3 6.3.1
Temperature -25C Transmitter
VDD = 1.8V Min Typ 7 -1 3 RMS DEVM 10 15 20 99% DEVM Peak DEVM Temperature = -25C Max Bluetooth Specification -6 to +4 10 13 20 25
(5) (5) (5) (2)
Radio Characteristics
Unit dBm dB
Maximum RF transmit power Relative transmit power
(3) (3) www..com Carrier frequency stability
(1)
-4 to +1
_aiEceEQJbniEea~a Product Data Sheet
kHz % % %
Modulation Accuracy
(3)(4)
Notes:
Results shown are referenced to input of the RF balun
(1)
BlueCore4-External firmware maintains the transmit power to be within the Bluetooth specification v1.2 limits Class 2 RF transmit power range, Bluetooth specification v1.2 Measurements methods are in accordance with the EDR RF Test Specification v0.9 Modulation accuracy utilises differential error vector magnitude (DEVM) with tracking of the carrier frequency drift. The Bluetooth specification values are for 8DPSK modulation (values for the /4 DQPSK modulation are less stringent)
(2) (3) (4)
(5)
6.3.2
Receiver
VDD = 1.8V Temperature = -25C Min Typ -87 -80 -10 -10 Max Bluetooth Specification -70 -70 -20 -20 Unit dBm dBm dBm dBm
Radio Characteristics
Modulation Sensitivity at 0.01% BER
(1)
/4 DQPSK 8DPSK /4 DQPSK 8DPSK
Maximum received signal at (1) 0.1% BER
Notes:
Results shown are referenced to input of the RF balun
(1)
Measurements methods are in accordance with the EDR RF Test Specification v0.9
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Radio Characteristics - Enhanced Data Rate
6.4 6.4.1
Temperature +85C Transmitter
VDD = 1.8V Min Typ 1 -1 3 RMS DEVM 10 15 20 99% DEVM Peak DEVM Temperature = +85C Max Bluetooth Specification -6 to +4 10 13 20 25
(5) (5) (5) (2)
Radio Characteristics
Unit dBm dB
Maximum RF transmit power Relative transmit power
(3) (3) www..com Carrier frequency stability
(1)
-4 to +1
_aiEceEQJbniEea~a Product Data Sheet
kHz % % %
Modulation Accuracy
(3)(4)
Notes:
Results shown are referenced to input of the RF balun
(1)
BlueCore4-External firmware maintains the transmit power to be within the Bluetooth specification v1.2 limits Class 2 RF transmit power range, Bluetooth specification v1.2 Measurements methods are in accordance with the EDR RF Test Specification v0.9 Modulation accuracy utilises differential error vector magnitude (DEVM) with tracking of the carrier frequency drift. The Bluetooth specification values are for 8DPSK modulation (values for the /4 DQPSK modulation are less stringent)
(2) (3) (4)
(5)
6.4.2
Receiver
VDD = 1.8V Temperature = +85C Min Typ -84 -77 0 -3 Max Bluetooth Specification -70 -70 -20 -20 Unit dBm dBm dBm dBm
Radio Characteristics
Modulation Sensitivity at 0.01% BER
(1)
/4 DQPSK 8DPSK /4 DQPSK 8DPSK
Maximum received signal at (1) 0.1% BER
Notes:
Results shown are referenced to input of the RF balun
(1)
Measurements methods are in accordance with the EDR RF Test Specification v0.9
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Radio Characteristics - Enhanced Data Rate
6.5 6.5.1
Temperature +105C Transmitter
VDD = 1.8V Min Typ -1 -1 3 RMS DEVM 10 15 20 99% DEVM Peak DEVM Temperature = +105C Max Bluetooth Specification -6 to +4 10 13 20 25
(5) (5) (5) (2)
Radio Characteristics
Unit dBm dB
Maximum RF transmit power Relative transmit power
(1) (1) www..com Carrier frequency stability
(1)
-4 to +1
_aiEceEQJbniEea~a Product Data Sheet
kHz % % %
Modulation Accuracy
(1)(2)
Notes:
Results shown are referenced to input of the RF balun
(1)
BlueCore4-External firmware maintains the transmit power to be within the Bluetooth specification v1.2 limits Class 2 RF transmit power range, Bluetooth specification v1.2 Measurements methods are in accordance with the EDR RF Test Specification v0.9 Modulation accuracy utilises differential error vector magnitude (DEVM) with tracking of the carrier frequency drift. The Bluetooth specification values are for 8DPSK modulation (values for the /4 DQPSK modulation are less stringent)
(2) (3) (4)
(5)
6.5.2
Receiver
VDD = 1.8V Temperature = +105C Min Typ -83 -76 0 -1 Max Bluetooth Specification -70 -70 -20 -20 Unit dBm dBm dBm dBm
Radio Characteristics
Modulation Sensitivity at 0.01% BER
(1)
/4 DQPSK 8DPSK /4 DQPSK 8DPSK
Maximum received signal at (1) 0.1% BER
Notes:
Results shown are referenced to input of the RF balun
(1)
Measurements methods are in accordance with the EDR RF Test Specification v0.9
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7
www..com
VDD_USB
A[18:0] D[15:0]
VDD_ANA
VDD_RADIO VDD_MEM VDD_CORE VDD_PADS VREG_EN TEST_EN VREG_IN RESETB WEB REB CSB In En USB RAM USB_DN Burst Mode Controller External Memory Driver Memory Mapped Control Status VREG Out
XTAL_OUT
XTAL_IN
_aiEceEQJbniEea~a Product Data Sheet
BC417143B-ds-001Pc
Baseband and Logic
USB_DP SPI_CSB SPI_CLK SPI_MOSI SPI_MISO UART_TX ADC Memory Management Unit UART UART_RX UART_RTS UART_CTS PCM_OUT Audio PCM Interface IQ MOD PA DAC PCM_IN PCM_SYNC PCM_CLK Physical Layer Hardware Engine IQ DEMOD Demodulator ATTENUATOR
PIO[0]/RXEN
Clock Generation
RF_IN
Device Diagram
LNA
Synchronous Serial Interface
RSSI ADC
RF Receiver
TX_A
TX_B
Microcontroller
VDD_PIO PIO[2] PIO[3]
RF Transmitter
+45 -45 /N/N+1 Fref Tune RF Synthesiser Interrupt Controller
PIO[4] PIO[5] PIO[6] PIO[7] RISC Microcontroller Programmable I/O PIO[8] PIO[9] PIO[10]
PIO[1]/TXEN
Loop Filter
Figure 7.1: BlueCore4-External Device Diagram
(c) Copyright Cambridge Silicon Radio Limited 2004 Pre-Production Information
Event Timer VSS_LO VDD_LO VSS_DIG VSS_ANA
RF Synthesiser
PIO[11]
AIO
AIO[2]
AIO[1]
AIO[0]
VSS_RADIO
Device Diagram
Page 38 of 107
Description of Functional Blocks
8
8.1
Description of Functional Blocks
RF Receiver
www..com
The receiver features a near-zero Intermediate Frequency (IF) architecture that allows the channel filters to be integrated on to the die. Sufficient out-of-band blocking specification at the Low Noise Amplifier (LNA) input allows the radio to be used in close proximity to Global System for Mobile Communications (GSM) and Wideband Code Division Multiple Access (W-CDMA) cellular phone transmitters without being desensitised. The use of a digital Frequency Shift Keying (FSK) discriminator means that no discriminator tank is needed and its excellent performance in the presence of noise allows BlueCore4-External to exceed the Bluetooth requirements for co-channel and adjacent channel rejection. For EDR, an ADC is used to digitise the IF received signal.
_aiEceEPJjiaiaaECa~ Product Data Sheet _aiEceEQJbniEea~a Product Data Sheet
8.1.1
Low Noise Amplifier
The LNA can be configured to operate in single-ended or differential mode. Single-ended mode is used for Class 1 Bluetooth operation; differential mode is used for Class 2 operation.
8.1.2
Analogue to Digital Converter
The Analogue to Digital Converter (ADC) is used to implement fast Automatic Gain Control (AGC). The ADC samples the Received Signal Strength Indicator (RSSI) voltage on a slot-by-slot basis. The front-end LNA gain is changed according to the measured RSSI value, keeping the first mixer input signal within a limited range. This improves the dynamic range of the receiver, improving performance in interference limited environments.
8.2 8.2.1
RF Transmitter IQ Modulator
The transmitter features a direct IQ modulator to minimise the frequency drift during a transmit timeslot, which results in a controlled modulation index. Digital baseband transmit circuitry provides the required spectral shaping.
8.2.2
Power Amplifier
The internal Power Amplifier (PA) has a maximum output power of +6dBm allowing BlueCore4-External to be used in Class 2 and Class 3 radios without an external RF PA. Support for transmit power control allows a simple implementation for Class 1 with an external RF PA.
8.3
RF Synthesiser
The radio synthesiser is fully integrated onto the die with no requirement for an external Voltage Controlled Oscillator (VCO) screening can, varactor tuning diodes, LC resonators or loop filter. The synthesiser is guaranteed to lock in sufficient time across the guaranteed temperature range to meet the Bluetooth specification v1.2.
8.4
Clock Input and Generation
The reference clock for the system is generated from a TCXO or crystal input between 8 and 40MHz. All internal reference clocks are generated using a phase locked loop, which is locked to the external reference frequency.
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Description of Functional Blocks
8.5 8.5.1
Baseband and Logic Memory Management Unit
The Memory Management Unit (MMU) provides a number of dynamically allocated ring buffers that hold the data which is in transit between the host and the air. The dynamic allocation of memory ensures efficient use of the available Random Access Memory (RAM) and is performed by a hardware MMU to minimise the overheads on the processor during data/voice transfers.
8.5.2
Burst Mode Controller
_aiEceEPJjiaiaaECa~ Product Data Sheet _aiEceEQJbniEea~a Product Data Sheet
During radio transmission the Burst Mode Controller (BMC) constructs a packet from header information www..com
previously loaded into memory-mapped registers by the software and payload data/voice taken from the appropriate ring buffer in the RAM. During radio reception, the BMC stores the packet header in memory-mapped registers and the payload data in the appropriate ring buffer in RAM. This architecture minimises the intervention required by the processor during transmission and reception.
8.5.3
Physical Layer Hardware Engine DSP
Dedicated logic is used to perform the following: Forward error correction Header error control Cyclic redundancy check Encryption Data whitening Access code correlation Audio transcoding The following voice data translations and operations are performed by firmware: A-law/-law/linear voice data (from host) A-law/-law/Continuously Variable Slope Delta (CVSD) (over the air) Voice interpolation for lost packets Rate mismatches The hardware supports all optional and mandatory features of Bluetest v1.2 including AFH and eSCO.
8.5.4
RAM
48Kbytes of on-chip RAM is provided to support the RISC MCU and is shared between the ring buffers used to hold voice/data for each active connection and the general purpose memory required by the Bluetooth stack.
8.5.5
External Memory Driver
The External Memory Driver interface can be used to connect to the external Flash memory and also to the optional external RAM for memory intensive applications.
8.5.6
USB
This is a full speed Universal Serial Bus (USB) interface for communicating with other compatible digital devices. BlueCore4-External acts as a USB peripheral, responding to requests from a Master host controller such as a PC.
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Description of Functional Blocks
8.5.7
Synchronous Serial Interface
This is a synchronous serial port interface (SPI) for interfacing with other digital devices. The SPI port can be used for system debugging. It can also be used for programming the Flash memory.
8.5.8
UART
This is a standard Universal Asynchronous Receiver Transmitter (UART) interface for communicating with other serial devices.
8.5.9
www..com
Audio PCM Interface
_aiEceEPJjiaiaaECa~ Product Data Sheet _aiEceEQJbniEea~a Product Data Sheet
The audio pulse code modulation (PCM) Interface supports continuous transmission and reception of PCM encoded audio data over Bluetooth.
8.6
Microcontroller
The microcontroller (MCU), interrupt controller and event timer run the Bluetooth software stack and control the radio and host interfaces. A 16-bit reduced instruction set computer (RISC) microcontroller is used for low power consumption and efficient use of memory.
8.6.1
Programmable I/O
BlueCore4-External has a total of 15 (12 digital and 3 analogue) programmable I/O terminals. These are controlled by firmware running on the device.
8.6.2
802.11 Coexistence Interface
Dedicated hardware is provided to implement a variety of coexistence schemes. Channel skipping AFH, priority signalling, channel signalling and host passing of channel instructions are all supported. The features are configured in firmware. Since the details of some methods are proprietary (e.g. Intel WCS) please contact CSR for details.
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CSR Bluetooth Software Stacks
9
CSR Bluetooth Software Stacks
BlueCore4-External is supplied with Bluetooth v1.2 compliant stack firmware, which runs on the internal RISC microcontroller. The BlueCore4-External software architecture allows Bluetooth processing and the application program to be shared in different ways between the internal RISC microcontroller and an external host processor (if any). The upper layers of the Bluetooth stack (above HCI) can be run either on-chip or on the host processor.
9.1
www..com
BlueCore HCI Stack
_aiEceEQJbniEea~a Product Data Sheet
External Flash
HCI LM LC
48KB RAM
Baseband MCU
USB Host UART Host I/O Radio
PCM I/O
Figure 9.1: BlueCore HCI Stack In the implementation shown in Figure 9.1 the internal processor runs the Bluetooth stack up to the Host Controller Interface (HCI). The Host processor must provide all upper layers including the application.
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CSR Bluetooth Software Stacks
9.1.1
Key Features of the HCI Stack - Standard Bluetooth Functionality
New Bluetooth v1.2 Mandatory Functionality: Adaptive frequency hopping (AFH), including classifier Faster connection - enhanced inquiry scan (immediate FHS response) LMP improvements Parameter ranges Optional v1.2 functionality supported:
_aiEceEQJbniEea~a Product Data Sheet
www..com Adaptive Frequency Hopping (AFH) as Master and Automatic Channel Classification
Fast Connect - Interlaced Inquiry and Page Scan plus RSSI during Inquiry Extended SCO (eSCO), eV3 +CRC, eV4, eV5 SCO handle Synchronisation The firmware has been written against the Bluetooth Core Specification v1.2. Bluetooth components: Baseband (including LC) LM HCI Standard USB v2.0 (full speed) and UART HCI Transport Layers All standard radio packet types Full Bluetooth data rate, enhanced data rates of 2 and 3Mbps Operation with up to seven active slaves Scatternet v2.5 operation Maximum number of simultaneous active ACL connections: 7
(2) (2) (1) (1)
Maximum number of simultaneous active SCO connections: 3
Operation with up to three SCO links, routed to one or more slaves All standard SCO voice coding, plus "transparent SCO" Standard operating modes: page, inquiry, page-scan and inquiry-scan All standard pairing, authentication, link key and encryption operations Standard Bluetooth power saving mechanisms: Hold, Sniff and Park modes, including "Forced Hold" Dynamic control of peers' transmit power via LMP Master/Slave switch Broadcast Channel quality driven data rate All standard Bluetooth Test Modes The firmware's supported Bluetooth features are detailed in the standard Protocol Implementation Conformance Statement (PICS) documents, available from http://www.csr.com.
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CSR Bluetooth Software Stacks
Note:
(1) (2)
Supports basic data rate up to 723.2kbps asymmetric, maximum allowed by Bluetooth specification v1.2 BlueCore4-External supports all combinations of active ACL and SCO channels for both Master and Slave operation, as specified by the Bluetooth specification v1.2
9.1.2
Key Features of the HCI Stack - Extra Functionality
The firmware extends the standard Bluetooth functionality with the following features: Supports BlueCore Serial Protocol (BCSP) - a proprietary, reliable alternative to the standard Bluetooth UART Host Transport
www..com Provides a set of approximately 50 manufacturer-specific HCI extension commands. This command set
_aiEceEQJbniEea~a Product Data Sheet
(called BCCMD - "BlueCore Command"), provides: Access to the chip's general-purpose PIO port
The negotiated effective encryption key length on established Bluetooth links Access to the firmware's random number generator Controls to set the default and maximum transmit powers - these can help minimise interference between overlapping, fixed-location piconets Dynamic UART configuration Radio transmitter enable/disable - a simple command connects to a dedicated hardware switch that determines whether the radio can transmit The firmware can read the voltage on a pair of the chip's external pins. This is normally used to build a battery monitor, using either VM or host code A block of BCCMD commands provides access to the chip's "persistent store" configuration database (PS). The database sets the device's Bluetooth address, Class of Device, radio (transmit class) configuration, SCO routing, LM, USB and DFU constants, etc. A UART "break" condition can be used in three ways: 1. 2. 3. Presenting a UART break condition to the chip can force the chip to perform a hardware reboot Presenting a break condition at boot time can hold the chip in a low power state, preventing normal initialisation while the condition exists With BCSP, the firmware can be configured to send a break to the host before sending data - normally used to wake the host from a deep sleep state
The DFU standard has been extended with public/private key authentication, allowing manufacturers to control the firmware that can be loaded onto their Bluetooth modules A modified version of the DFU protocol allows firmware upgrade via the chip's UART A block of "radio test" or BIST commands allows direct control of the chip's radio. This aids the development of modules' radio designs, and can be used to support Bluetooth qualification. Virtual Machine (VM). The firmware provides the VM environment in which to run application-specific code. Although the VM is mainly used with BlueLab and "RFCOMM builds" (alternative firmware builds providing L2CAP, SDP and RFCOMM), the VM can be used with this build to perform simple tasks such as flashing LED's via the chip's PIO port. Hardware low power modes: shallow sleep and deep sleep. The chip drops into modes that significantly reduce power consumption when the software goes idle. SCO channels are normally routed via HCI (over BCSP). However, up to three SCO channels can be routed over the chip's single PCM port (at the same time as routing any remaining SCO channels over HCI). Co-operative existence with 802.11b/g chipsets. The device can be optionally configured to support a number of different co-existence schemes including: TDMA - Bluetooth and WLAN avoid transmitting at the same time. FDMA - Bluetooth avoids transmitting within the WLAN channel
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CSR Bluetooth Software Stacks
Combination TDMA & FDMA - Bluetooth avoids transmitting in the WLAN channel only when WLAN is active. Please refer to separate documentation for full details of the co-existence schemes that CSR supports.
Note:
Always refer to the Firmware Release Note for the specific functionality of a particular build.
_aiEceEQJbniEea~a Product Data Sheet
www..com
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CSR Bluetooth Software Stacks
9.2
BlueCore RFCOMM Stack
RFCOMM External Flash L2CAP HCI LM LC SDP
_aiEceEQJbniEea~a Product Data Sheet
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48KB RAM
Baseband MCU
USB Host UART Host I/O Radio
PCM I/O
Figure 9.2: BlueCore RFCOMM Stack In the version of the firmware, shown in Figure 9.2 the upper layers of the Bluetooth stack up to RFCOMM are run on-chip. This reduces host-side software and hardware requirements at the expense of some of the power and flexibility of the HCI only stack.
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CSR Bluetooth Software Stacks
9.2.1
Key Features of the BlueCore4-External RFCOMM Stack
Interfaces to Host: RFCOMM, an RS-232 serial cable emulation protocol SDP, a service database look-up protocol Connectivity: Maximum number of active slaves: 3 Maximum number of simultaneous active ACL connections: 3
_aiEceEQJbniEea~a Product Data Sheet
www..com Maximum number of simultaneous active SCO connections: 3
Data Rate: up to 350kbps Security:
(1)
Full support for all Bluetooth security features up to and including strong (128-bit) encryption. Power Saving: Full support for all Bluetooth power saving modes (Park, Sniff and Hold). Data Integrity: CQDDR increases the effective data rate in noisy environments. RSSI used to minimise interference to other radio devices using the ISM band.
Note:
(1)
The data rate is with respect to BlueCore4-External with basic data rate packets.
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CSR Bluetooth Software Stacks
9.3
BlueCore Virtual Machine Stack
VM Application Software External Flash RFCOMM L2CAP HCI LM SDP
_aiEceEQJbniEea~a Product Data Sheet
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LC
48KB RAM
Baseband MCU
USB Host (Optional) UART Host I/O Radio
PCM I/O
Figure 9.3: Virtual Machine In Figure 9.3, this version of the stack firmware shown requires no host processor (but can use a host processor for debugging etc.). All software layers, including application software, run on the internal RISC processor in a protected user software execution environment known as a Virtual Machine (VM). The user may write custom application code to run on the BlueCore VM using BlueLabTM software development kit (SDK) supplied with the BlueLab Multimedia and Casira development kits, available separately from CSR. This code will then execute alongside the main BlueCore firmware. The user is able to make calls to the BlueCore firmware for various operations. The execution environment is structured so the user application does not adversely affect the main software routines, thus ensuring that the Bluetooth stack software component does not need re-qualification when the application is changed. Using the VM and the BlueLab SDK the user is able to develop applications such as a cordless headset or other profiles without the requirement of a host controller. BlueLab is supplied with example code including a full implementation of the headset profile.
Note:
Sample applications to control PIO lines can also be written with BlueLab SDK and the VM for the HCI stack.
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CSR Bluetooth Software Stacks
9.4
BlueCore HID Stack
VM Application Software External Flash HID L2CAP HCI LM SDP
_aiEceEQJbniEea~a Product Data Sheet
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LC
48KB RAM
Baseband MCU
Sensing Hardware (Optical Sensor etc.)
PIO/UART
HID I/O
Radio
Figure 9.4: HID Stack This version of the stack firmware requires no host processor. All software layers, including application software, run on the internal RISC microcontroller in a protected user software execution environment known as a virtual machine (VM). The user may write custom application code to run on the BlueCore VM using BlueLab Professional software development kit (SDK) supplied with the BlueLab Professional and Casira development kits, available separately from CSR. This code will then execute alongside the main BlueCore firmware. The user is able to make calls to the BlueCore firmware for various operations. The execution environment is structured so the user application does not adversely affect the main software routines, thus ensuring that the Bluetooth stack software component does not need re-qualification when the application is changed. Using the VM and the BlueLab Professional SDK the user is able to develop Bluetooth HID devices such as an optical mouse or keyboard. The user is able to customise features such as power management and connect/reconnect behaviour. The HID I/O component in the HID stack controls low latency data acquisition from external sensor hardware. With this component running in native code, it does not incur the overhead of the VM code interpreter. Supported external sensors include 5 mouse buttons, the Agilent ADNS-2030 optical sensor, quadrature scroll wheel, direct coupling to a keyboard matrix and a UART interface to custom hardware. A reference schematic for implementing a three button, optical mouse with scroll wheel is available from CSR.
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CSR Bluetooth Software Stacks
9.5
BCHS Software
BlueCore Embedded Host Software is designed to enable CSR customers to implement Bluetooth functionality into embedded products quickly, cheaply and with low risk. BCHS is developed to work with CSR's family of BlueCore IC's. BCHS is intended for embedded products that have a host processor for running BCHS and the Bluetooth application e.g. a mobile phone or a PDA. BCHS together with the BlueCore IC with embedded Bluetooth core stack (L2CAP, RFCOMM and SDP) is a complete Bluetooth system solution from RF to profiles. BCHS includes most of the Bluetooth intelligence and gives the user a simple API. This makes it possible to develop a Bluetooth product without in-depth Bluetooth knowledge.
_aiEceEQJbniEea~a Product Data Sheet
www..com
The BlueCore Embedded Host Software contains 3 elements: Example Drivers (BCSP and proxies) Bluetooth Profile Managers Example Applications The profiles are qualified which makes the qualification of the final product very easy. BCHS is delivered with source code (ANSI C). With BCHS also come example applications in ANSI C, which makes the process of writing the application easier.
9.6
Additional Software for Other Embedded Applications
When the upper layers of the Bluetooth protocol stack are run as firmware on BlueCore4-External, a UART software driver is supplied that presents the L2CAP, RFCOMM and Service Discovery (SDP) APIs to higher Bluetooth stack layers running on the host. The code is provided as `C' source or object code.
9.7
CSR Development Systems
CSR's BlueLab and Casira development kits are available to allow the evaluation of the BlueCore4-External hardware and software, and as toolkits for developing on-chip and host software.
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Enhanced Data Rate
10 Enhanced Data Rate
EDR has been introduced to provide 2x and optionally 3x data rates with minimal disruption to higher layers of the Bluetooth stack. CSR supports both of the new data rates, with BlueCore4-External. BlueCore4-External is compliant with revision v0.9 of the specification.
10.1
Enhanced Data Rate Baseband
At the baseband level EDR uses the same 1.6kHz slot rate as basic data rate and therefore the packets can be 1, 3, or 5 slots long as per the basic data rate. Where EDR differs from the basic data rate is that in the same 1MHz symbol rate 2 or 3bits are used per symbol, compared to 1bit per symbol used by the basic data rate. To www..com achieve the increase in number of bits symbol, two new modulation schemes have been introduced as summarised in Table 10.1 and the modulation schemes are explained further in Section 10.2 and Section 0. Data Rate Scheme Basic data rate EDR EDR Bits Per Symbol 1 2 3 Modulation GFSK /4 DQPSK 8DPSK (optional)
_aiEceEQJbniEea~a Product Data Sheet
Table 10.1: Data Rate Schemes Although the EDR uses new packets Link establishment and management are unchanged and still use Basic Rate packets
10.2
Enhanced Data Rate /4 DQPSK
8-state Differential Phase Shift Keying 2 bits determine phase shift between consecutive symbols 2 bits determine phase shift between consecutive symbols /4 rotation avoids phase shift of , which would cause large amplitude variation Raised Cosine pulse shaping filter to further reduce side band emissions Bit Pattern 00 01 11 10 Phase Shift /4 3/4 -3/4 -/4 Table 10.2: 2 bits determine phase shift between consecutive symbols
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Enhanced Data Rate
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Table 10.3: /4 DQPSK
10.3
Enhanced Data Rate 8DPSK
8-state Differential Phase-Shift Keying Three bits determine phase shift between consecutive symbols Bit Pattern 000 001 011 010 110 111 101 100 Phase Shift 0 /4 /2 3/4 -3/4 -/2 -/4 Table 10.4: 3 bits determine phase shift between consecutive symbols
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Device Terminal Descriptions
11 Device Terminal Descriptions
11.1 RF Ports
The BlueCore4-External RF_IN terminal can be configured as either a single ended or differential input. The operational mode is determined by the setting the PS Key PSKEY_TXRX_PIO_CONTROL (0x20).
11.1.1 TX_A and TX_B
TX_A and TX_B form a complementary balanced pair. On transmit; their outputs are combined using a balun into the www..com single-ended output required for the antenna. Similarly, on receive their input signals are combined internally.
_aiEceEQJbniEea~a Product Data Sheet
Both terminals present similar complex impedances that require matching networks between them and the balun. Starting from the substrate (chip side), the outputs can each be modelled as an ideal current source in parallel with a lossy resistance and a capacitor. The bond wire can be represented as series inductance.
BlueCore4-External
P A
_
PA
L2 1.5nH
+
RF Switch
R2 10
0.9pF
L3 1.5nH
RF Switch
R3 10
+
LNA
_
0.9pF
Figure 11.1: Circuit TX/RX_A and TX/RX_B
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Device Terminal Descriptions
11.1.2 Single-Ended Input (RF_IN)
This is the single ended RF input from the antenna. The input presents a complex impedance that requires a matching network between the terminal and the antenna. Starting from the substrate (chip) side, the input can be modelled as a lossy capacitor with the bond wire to the ball grid represented as a series inductance. The terminal is DC blocked. The DC level must not exceed (VSS_RADIO -0.3V to VDD_RADIO + 0.3V).
BlueCore4-External
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L1 1.5nH R1 6.8 C1 0.68pF
_aiEceEQJbniEea~a Product Data Sheet
RF_IN
Figure 11.2: Circuit RF_IN
Note:
Both terminals must be externally DC biased to VDD_RADIO.
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Device Terminal Descriptions
11.2
External Reference Clock Input (XTAL_IN)
The BlueCore4-External RF local oscillator and internal digital clocks are derived from the reference clock at the BlueCore4-External XTAL_IN input. This reference may be either an external clock or from a crystal connected between XTAL_IN and XTAL_OUT. The crystal mode is described in Section 11.2.5.
11.2.1 External Mode
BlueCore4-External can be configured to accept an external reference clock (from another device, such as TCXO) at XTAL_IN by connecting XTAL_OUT to ground. The external clock can either be a digital level square wave or sinusoidal and this may be directly coupled to XTAL_IN without the need for additional components. If the peaks of the reference clock are below VSS_ANA or above VDD_ANA, it must be driven through a DC www..com blocking capacitor (~33pF) connected to XTAL_IN. A digital level reference clock gives superior noise immunity as the high slew rate clock edges have lower voltage to phase conversion. The external clock signal should meet the specifications in Table 11.1: Min Frequency Duty cycle Edge Jitter (At Zero Crossing) Signal Level
(1)
_aiEceEQJbniEea~a Product Data Sheet
Typ 16MHz 50:50 -
Max 40MHz 80:20 15ps rms VDD_ANA
(2)(3)
7.5MHz 20:80 400mV pk-pk
Table 11.1: External Clock Specifications
Notes:
(1) (2) (3)
The frequency should be an integer multiple of 250kHz except for the CDMA/3G frequencies VDD_ANA is 1.8V nominal If the external clock is driven through a DC blocking capacitor then maximum allowable amplitude is reduced from VDD_ANA to 800mV pk-pk
11.2.2 XTAL_IN Impedance in External Mode
The impedance of the XTAL_IN will not change significantly between operating modes, typically 10fF. When transitioning from deep sleep to an active state a spike of up to 1pC may be measured. For this reason it is recommended that a buffered clock input be used.
11.2.3 Clock Timing Accuracy
As Figure 11.3 indicates, the 250ppm timing accuracy on the external clock is required 7ms after the assertion of the system clock request line. This is to guarantee that the firmware can maintain timing accuracy in accordance with the Bluetooth v1.2 specification. Radio activity may occur after 11ms, therefore at this point, the timing accuracy of the external clock source must be within 20ppm.
Required TCXO Clock Accuracy 1000 ppm 250 ppm 20 ppm
CLK_REQ
0
5
7
11
ms After Clock Request
Figure 11.3: TCXO Clock Accuracy
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Device Terminal Descriptions
11.2.4 Clock Start-Up Delay
BlueCore4-External hardware incorporates an automatic 5ms delay after the assertion of the system clock request signal before running firmware. This is suitable for most applications using an external clock source. However, there may be scenarios where the clock cannot be guaranteed to either exist or be stable after this period. Under these conditions, BlueCore4-External firmware provides a software function which will extend the system clock request signal by a period stored in PSKEY_CLOCK_STARTUP_DELAY. This value is set in milliseconds from 5-31ms. This PS Key allows the designer to optimise a system where clock latencies may be longer than 5ms while still keeping the current consumption of BlueCore4-External as low as possible. BlueCore4-External will consume about 2mA of current for the duration of PSKEY_CLOCK_STARTUP_DELAY before activating the firmware.
_aiEceEQJbniEea~a Product Data Sheet
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Actual Allowable Clock Presence Delay on XTAL_IN vs. PSKey Setting
30.0
25.0
20.0
D elay (m s)
15.0
10.0
5.0
0.0 0.0 5.0 10.0 15.0 PSKEY_CLOCK_STARTUP_DELAY 20.0 25.0 30.0
Figure 11.4: Actual Allowable Clock Presence Delay on XTAL_IN vs. PS Key Setting
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Device Terminal Descriptions
11.2.5 Input Frequencies and PS Key Settings
BlueCore4-External should be configured to operate with the chosen reference frequency. This is accomplished by setting the PS Key PSKEY_ANA_FREQ (0x1fe) for all frequencies with an integer multiple of 250kHz. The input frequency default setting in BlueCore4-External is 26MHz. The following CDMA/3G TCXO frequencies are also catered for: 7.68, 14.4, 15.36, 16.2, 16.8, 19.2, 19.44, 19.68, 19.8 and 38.4MHz. Reference Crystal Frequency (MHz)
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PSKEY_ANA_FREQ (0x1fe) (Units of 1kHz) 7680 14400 15360 16200 16800 19200 19440 19680 19800 38400 26000
7.68 14.40 15.36 16.20 16.80 19.20 19.44 19.68 19.80 38.40 n x 250kHz +26.00 Default
_aiEceEQJbniEea~a Product Data Sheet
Table 11.2: PS Key Values for CDMA/3G Phone TCXO Frequencies
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Device Terminal Descriptions
11.3
Crystal Oscillator (XTAL_IN, XTAL_OUT)
The BlueCore4-External RF local oscillator and internal digital clocks are derived from the reference clock at the BlueCore4-External XTAL_IN input. This reference may be either an external clock or from a crystal connected between XTAL_IN and XTAL_OUT. The external reference clock mode is described in Section 11.2.
11.3.1 XTAL Mode
BlueCore4-External contains a crystal driver circuit. This operates with an external crystal and capacitors to form a Pierce oscillator.
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gm BlueCore4-External
-
_aiEceEQJbniEea~a Product Data Sheet
Ctrim
Cint
Ctrim
Ct2
Ct1
Figure 11.5: Crystal Driver Circuit Figure 11.6 shows an electrical equivalent circuit for a crystal. The crystal appears inductive near its resonant frequency. It forms a resonant circuit with its load capacitors.
Cm Lm Rm
Co
Figure 11.6: Crystal Equivalent Circuit The resonant frequency may be trimmed with the crystal load capacitance. BlueCore4-External contains variable internal capacitors to provide a fine trim. The BlueCore4-External driver circuit is a transconductance amplifier. A voltage at XTAL_IN generates a current at XTAL_OUT. The value of transconductance is variable and may be set for optimum performance.
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XTAL_OUT
XTAL_IN
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Device Terminal Descriptions
11.3.2 Load Capacitance
For resonance at the correct frequency the crystal should be loaded with its specified load capacitance, which is defined for the crystal. This is the total capacitance across the crystal viewed from its terminals. BlueCore4-External provides some of this load with the capacitors Ctrim and Cint. The remainder should be from the external capacitors labelled Ct1 and Ct2. Ct1 should be three times the value of Ct2 for best noise performance. This maximises the signal swing, hence slew rate at XTAL_IN, to which all on chip clocks are referred. Crystal load capacitance, Cl is calculated with the following equation: Cl = Cint +
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C trim C C + t1 t 2 2 C t1 + C t 2
Equation 11.1: Load Capacitance
_aiEceEQJbniEea~a Product Data Sheet
Where:
Ctrim = 3.4pF nominal (Mid range setting) Cint = 1.5pF
Note:
Cint does not include the crystal internal self capacitance, it is the driver self capacitance
11.3.3 Frequency Trim
BlueCore4-External enables frequency adjustments to be made. This feature is typically used to remove initial tolerance frequency errors associated with the crystal. Frequency trim is achieved by adjusting the crystal load capacitance with on chip trim capacitors, Ctrim. The value of Ctrim is set by a 6-bit word in the Persistent Store Key PSKEY_ANA_FTRIM (0x1f6). Its value is calculated thus: Ctrim = 110 fF x PSKEY_ANA_FTRIM Equation 11.2: Trim Capacitance There are two Ctrim capacitors, which are both connected to ground. When viewed from the crystal terminals, they appear in series so each least significant bit (LSB) increment of frequency trim presents a load across the crystal of 55fF. The frequency trim is described by Equation 11.3: (Fx ) = pullability x 55 x 10 -3 (ppm / LSB ) Fx Equation 11.3: Frequency Trim Where Fx is the crystal frequency and pullability is a crystal parameter with units of ppm/pF. Total trim range is 63 times the value above. If not specified, the pullability of a crystal may be calculated from its motional capacitance with Equation 11.4:
(Fx ) Cm = Fx (C) 4(Cl + C0 )2
Equation 11.4: Pullability
Where:
C0 = Crystal self capacitance (shunt capacitance) Cm = Crystal motional capacitance (series branch capacitance in crystal model). See Figure 11.6.
Note:
It is a Bluetooth requirement that the frequency is always within 20ppm. The trim range should be sufficient to pull the crystal within 5ppm of the exact frequency. This leaves a margin of 15ppm for frequency drift with ageing and temperature. A crystal with an ageing and temperature drift specification of better than 15ppm is required.
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Device Terminal Descriptions
11.3.4 Transconductance Driver Model
The crystal and its load capacitors should be viewed as a transimpedance element, whereby a current applied to one terminal generates a voltage at the other. The transconductance amplifier in BlueCore4-External uses the voltage at its input, XTAL_IN, to generate a current at its output, XTAL_OUT. Therefore, the circuit will oscillate if the transconductance, transimpedance product is greater than unity. For sufficient oscillation amplitude, the product should be greater than 3. The transconductance required for oscillation is defined by the following relationship: gm >
(2Fx ) Rm ((C0 + Cint )(Ct1 + Ct 2 + 2Ctrim ) + (Ct1 + Ctrim )(Ct2 + Ctrim ))2
2
3(Ct1 +Ctrim )(Ct 2 + Ctrim )
Equation 11.5: Transconductance Required for Oscillation
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_aiEceEQJbniEea~a Product Data Sheet
BlueCore4-External guarantees a transconductance value of at least 2mA/V at maximum drive level.
Notes:
More drive strength is required for higher frequency crystals, higher loss crystals (larger Rm) or higher capacitance loading. Optimum drive level is attained when the level at XTAL_IN is approximately 1V pk-pk. The drive level is determined by the crystal driver transconductance, by setting the Persistent Store KEY_XTAL_LVL (0x241).
11.3.5 Negative Resistance Model
An alternative representation of the crystal and its load capacitors is a frequency dependent resistive element. The driver amplifier may be considered as a circuit that provides negative resistance. For oscillation, the value of the negative resistance must be greater than that of the crystal circuit equivalent resistance. Although the BlueCore4-External crystal driver circuit is based on a transimpedance amplifier, an equivalent negative resistance may be calculated for it with the following formula in Equation 11.6: Rneg > gm (2Fx ) (C0 + Cint )((Ct1 + Ct 2 + 2Ctrim ) + (Ct1 + Ctrim )(Ct 2 + Ctrim ))2
2
3(Ct1 +Ctrim )(Ct 2 + Ctrim )
Equation 11.6: Equivalent Negative Resistance
This formula shows the negative resistance of the BlueCore4-External driver as a function of its drive strength. The value of the driver negative resistance may be easily measured by placing an additional resistance in series with the crystal. The maximum value of this resistor (oscillation occurs) is the equivalent negative resistance of the oscillator.
Min Typ Max
Frequency Initial Tolerance Pullability
8MHz -
16MHz 25ppm 20ppm/pF
32MHz -
Table 11.3: Oscillator Negative Resistance
11.3.6 Crystal PS Key Settings
See tables in Section 11.2.5.
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Device Terminal Descriptions
11.3.7 Crystal Oscillator Characteristics
Crystal Load Capacitance and Series Resistance Limits with Crystal Frequency
1000.0
Max Xtal Rm Value (ESR), (Ohm)
_aiEceEQJbniEea~a Product Data Sheet
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100.0
10.0 2.5 3.5 4.5 5.5 6.5 7.5 Load Capacitance (pF) 8.5 9.5 10.5 11.5 12.5
8 MHz 20 MHz 32 MHz
12 MHz 24 MHz
16 MHz 28 MHz
Figure 11.7: Crystal Load Capacitance and Series Resistance Limits with Crystal Frequency
Note:
Graph shows results for BlueCore4-External crystal driver at maximum drive level.
Conditions:
Ctrim = 3.4pF centre value Crystal Co = 2pF Transconductance setting = 2mA/V Loop gain = 3 Ct1/Ct2 = 3
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Device Terminal Descriptions
BlueCore4-External XTAL Driver Characteristics
0.007
0.006
0.005 Transconductance (S)
0.004
0.003
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0.002
0.001
0.000 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PSKEY_XTAL_LVL
Gm Typical Gm Minimum Gm Maximum
Figure 11.8: Crystal Driver Transconductance vs. Driver Level Register Setting
Note:
Drive level is set by Persistent Store Key PSKEY_XTAL_LVL (0x241).
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Device Terminal Descriptions
Negative Resistance for 16 MHz Xtal
10000
Max -ve Resistance ()
1000
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100
10 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 11.0 12.0 13.0 14.0 15.0 16.0 Drive Level Setting
Typical Minimum Maximum
Figure 11.9: Crystal Driver Negative Resistance as a Function of Drive Level Setting Crystal parameters:
Crystal frequency 16MHz (Please refer to your software build release note for frequencies supported); Crystal C0 = 0.75pF
Circuit parameters:
Ctrim = 8pF, maximum value Ct1,Ct2 = 5pF (3.9pF plus 1.1 pF stray) (Crystal total load capacitance 8.5pF)
Note:
This is for a specific crystal and load capacitance.
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Device Terminal Descriptions
11.4
Off-Chip Program Memory
The external memory port provides a facility to interface up to 8Mbits of 16-bit external memory. This off-chip storage is used to store BlueCore4-External settings and program code. Flash is the storage mechanism typically used by BlueCore4-External modules, however external masked-ROM may also be used if the host takes over responsibility for storing configuration data. The external memory port consists of 16 bi-directional data lines, D[15:0]; 19 output address lines, A[18:0] and three active low output control signals (WEB, CEB, REB). WEB is asserted when data is written to external memory. REB is asserted when data is read from external memory and the chip select line. CSB is asserted when any data transfer (read or write) is required. All of the external memory port connections are implemented using CMOS technology and use standard 0V and VDD_MEM (1.8-3.6V) signalling levels.
_aiEceEQJbniEea~a Product Data Sheet
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Parameter
Value
Data width Minimum total capacity Maximum access time
16-bit 4Mbit (256kWord) 90ns @125C 50pF load 110ns @85C 10pF load
Table 11.4: Flash Device Hardware Requirements
In addition to these hardware requirements, particular care should be taken to ensure that the sector organisation of the extended memory has the correct format. A sector is defined as an individually erasable area of external Flash. It is important to make sure that external memory devices meet certain minimum specifications. In addition particular care should be taken to ensure that the sector organisation of the extended memory has the correct format.
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Device Terminal Descriptions
11.4.1 Minimum Flash Specification
The flash device used with BlueCore4-External must meet the following criteria: Standard or extended form of either the JEDEC (AMD/Fujitsu/SST) or Intel command set. Access time must be 90ns @125C 50pF load or 110ns @85C 10pF load. Write strobe of 100ns. Accessible in word mode, i.e., via a 16-bit data bus. Support changing different bits within each word from 1 to 0 in at least two separate programming operations.
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Programming and erase times must have fixed upper limits. Must be bottom boot or uniform sector.
Must have independently erasable sectors with at least the following boundaries (see Memory Map for more information).
Word Address Size (kWords)
0x00000 - 0x01FFF 0x02000 - 0x02FFF 0x03000 - 0x03FFF 0x04000 - 0x07FFF 0x08000 - 0x0FFFF 0x10000 - 0x17FFF 0x18000 - ...
Table 11.5: Flash Sector Boundaries
Important Note:
8 4 4 16 32 32 Don't care
Satisfaction of these criteria is not sufficient for a particular device to be used; it must also support the Common Flash Interface described in Section 11.4.2 or be supported in the BlueCore4-External firmware and host-side tools.
11.4.2 Common Flash Interface
The firmware can adapt automatically to work with some flash devices. If in addition to satisfying the minimum Flash specification described above, they meet the following criteria: The device must support the Common Flash Interface, as defined by JEDEC standard JESD68. The device must return one of the following codes for either the Primary or Alternative Algorithm Command Set (offset 0x13b or 0x17 of the Query Structure Output):
Code Description
0x0001 0x0002 0x0003 0x0701
Intel/Sharp Extended Command Set AMD/Fujitsu Standard Command Set Intel Standard Command Set AMD/Fujitsu Extended Command Set
Table 11.6: Common Flash Interface Return Codes
The device must return one of the following patterns of Erase Block Region Information (beginning at offset 0x2d of the Query Structure Output):
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If any of these criteria is not met, then the device will not work unless the device is supported by the BlueCore4-External firmware.
11.4.3 Memory Timing
Memory Write Cycle Symbol Parameter Min
(1)
Typ
Max
(1)
Unit
twc tdat:su tdat:hd
www..com
Write cycle time Data set-up time Data hold time Address set-up time WEB low
300 150 150 150 100
-
-
ns ns ns ns ns
_aiEceEQJbniEea~a Product Data Sheet
taddr:su twe:low
Table 9.7: Memory Write Cycle
Note:
(1)
Valid for temperatures between -40C and +105C
twc A[18:0] Address Valid
CSB
tdat:hd
t addr:su WEB
twe:low
REB
t dat:su D[15:0] Data Valid
Figure 11.10: Memory Write Cycle
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Device Terminal Descriptions
Memory Read Cycle Symbol Parameter Min
(1)
Typ
Max
(1)
Unit
trc taa tre tdat:hd
Read cycle time Address access time Read enable access time Data hold time from address line
114 0
125 -
110 110 -
ns ns ns ns
Table 9.8: Memory Read Cycle
Note: www..com (1)
_aiEceEQJbniEea~a Product Data Sheet
Valid for temperatures between -40C and +105C
trc A[18:0] taa
CSB
REB
tre WEB
tdat:hd D[15:0] Data Valid Data Valid
Figure 11.11: Memory Read Cycle
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11.5 UART Interface
BlueCore4-External Universal Asynchronous Receiver Transmitter (UART) interface provides a simple (1) mechanism for communicating with other serial devices using the RS232 standard .
BlueCore4-External
UART_TX
www..com
UART_RX UART_RTS UART_CTS
_aiEceEQJbniEea~a Product Data Sheet
Figure 11.12: Universal Asynchronous Receiver
Four signals are used to implement the UART function, as shown in Figure 11.12. When BlueCore4-External is connected to another digital device, UART_RX and UART_TX transfer data between the two devices. The remaining two signals, UART_CTS and UART_RTS, can be used to implement RS232 hardware flow control where both are active low indicators. All UART connections are implemented using CMOS technology and have signalling levels of 0V and VDD_PADS. UART configuration parameters, such as Baud rate and packet format, are set using BlueCore4-External software.
Notes:
In order to communicate with the UART at its maximum data rate using a standard PC, an accelerated serial port adapter card is required for the PC.
(1)
Uses RS232 protocol but voltage levels are 0V to VDD_USB, (requires external RS232 transceiver chip)
Parameter Possible Values
Baud Rate Flow Control Parity Number of Stop Bits Bits per channel
Minimum Maximum
1200 Baud (2%Error) 9600 Baud (1%Error) 1.5MBaud (1%Error) RTS/CTS or None None, Odd or Even 1 or 2 8
Table 11.7: Possible UART Settings
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The UART interface is capable of resetting BlueCore4-External upon reception of a break signal. A Break is identified by a continuous logic low (0V) on the UART_RX terminal, as shown in Figure 11.13. If tBRK is longer than the value, defined by the PS Key PSKEY_HOST_IO_UART_RESET_TIMEOUT, (0x1a4), a reset will occur. This feature allows a host to initialise the system to a known state. Also, BlueCore4-External can emit a Break character that may be used to wake the Host.
t UART RX
BRK
Figure 11.13: Break Signal
Note: www..com The DFU boot loader must be loaded into the Flash device before the UART or USB interfaces can be used.
_aiEceEQJbniEea~a Product Data Sheet
This initial flash programming can be done via the SPI. Table 11.3 shows a list of commonly used Baud rates and their associated values for the Persistent Store Key PSKEY_UART_BAUD_RATE (0x204). There is no requirement to use these standard values. Any Baud rate within the supported range can be set in the Persistent Store Key according to the formula in Equation 11.7.
Baud Rate = PSKEY_UART_BAUD_RATE 0.004096
Equation 11.7: Baud Rate
Persistent Store Value Baud Rate Hex Dec Error
1200 2400 4800 9600 19200 38400 57600 76800 115200 230400 460800 921600 1382400
0x0005 0x000a 0x0014 0x0027 0x004f 0x009d 0x00ec 0x013b 0x01d8 0x03b0 0x075f 0x0ebf 0x161e
5 10 20 39 79 157 236 315 472 944 1887 3775 5662
1.73% 1.73% 1.73% -0.82% 0.45% -0.18% 0.03% 0.14% 0.03% 0.03% -0.02% 0.00% -0.01%
Table 11.8: Standard Baud Rates
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11.5.1 UART Bypass
RESET RXD CTS RTS TXD UART_TX UART_RTS UART_CTS UART_RX PIO4 PIO5 PIO6 PIO7 TX RTS CTS RX
_aiEceEQJbniEea~a Product Data Sheet
www..com Host Processor
UART
Another Device
BlueCore4-External
Test Interface
Figure 11.14: UART Bypass Architecture
11.5.2 UART Configuration While RESET is Active
The UART interface for BlueCore4-External while the chip is being held in reset is tri-state. This will allow the user to daisy chain devices onto the physical UART bus. The constraint on this method is that any devices connected to this bus must tri-state when BlueCore4-External reset is de-asserted and the firmware begins to run.
11.5.3 UART Bypass Mode
Alternatively, for devices that do not tri-state the UART bus, the UART bypass mode on BlueCore4-External can be used. The default state of BlueCore4-External after reset is de-asserted, this is for the host UART bus to be connected to the BlueCore4-External UART, thereby allowing communication to BlueCore4-External via the UART. In order to apply the UART bypass mode, a BCCMD command will be issued to BlueCore4-External upon this, it will switch the bypass to PIO[7:4] as shown in Figure 11.14. Once the bypass mode has been invoked, BlueCore4-External will enter the deep sleep state indefinitely. In order to re-establish communication with BlueCore4-External, the chip must be reset so that the default configuration takes affect. It is important for the host to ensure a clean Bluetooth disconnection of any active links before the bypass mode is invoked. Therefore it is not possible to have active Bluetooth links while operating the bypass mode.
11.5.4 Current Consumption in UART Bypass Mode
The current consumption for a device in UART Bypass Mode is equal to the values quoted for a device in standby mode.
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11.6
USB Interface
BlueCore4-External USB devices contain a full speed (12Mbits/s) USB interface that is capable of driving a USB cable directly. No external USB transceiver is required. The device operates as a USB peripheral, responding to requests from a master host controller such as a PC. Both the OHCI and the UHCI standards are supported. The set of USB endpoints implemented can behave as specified in the USB section of the Bluetooth specification v1.2 or alternatively can appear as a set of endpoint appropriate to USB audio devices such as speakers. As USB is a Master/Slave oriented system (in common with other USB peripherals), BlueCore4-External only supports USB Slave operation.
www..com
11.6.1 USB Data Connections
The USB data lines emerge as pins USB_DP and USB_DN. These terminals are connected to the internal USB I/O buffers of the BlueCore4-External and therefore have a low output impedance. To match the connection to the characteristic impedance of the USB cable, resistors must be placed in series with USB_DP / USB_DN and the cable.
_aiEceEQJbniEea~a Product Data Sheet
11.6.2 USB Pull-Up Resistor
BlueCore4-External features an internal USB pull-up resistor. This pulls the USB_DP pin weakly high when BlueCore4-External is ready to enumerate. It signals to the PC that it is a full speed (12Mbit/s) USB device. The USB internal pull-up is implemented as a current source, and is compliant with Section 7.1.5 of the USB specification v1.2. The internal pull-up pulls USB_DP high to at least 2.8V when loaded with a 15k 5% pull-down resistor (in the hub/host) when VDD_PADS=3.1V. This presents a Thevenin resistance to the host of at least 900. Alternatively, an external 1.5k pull-up resistor can be placed between a PIO line and D+ on the USB cable. The firmware must be alerted to which mode is used by setting PS Key PSKEY_USB_PIO_PULLUP appropriately. The default setting uses the internal pull-up resistor.
11.6.3 Power Supply
The USB specification dictates that the minimum output high voltage for USB data lines is 2.8V. To safely meet the USB specification, the voltage on the VDD_USB supply terminals must be an absolute minimum of 3.1V. CSR recommends 3.3V for optimal USB signal quality.
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11.6.4 Self Powered Mode
In self powered mode, the circuit is powered from its own power supply and not from the VBUS (5V) line of the USB cable. It draws only a small leakage current (below 0.5mA) from VBUS on the USB cable. This is the easier mode for which to design for, as the design is not limited by the power that can be drawn from the USB hub or root port. However, it requires that VBUS be connected to BlueCore4-External via a resistor network (Rvb1 and Rvb2), so BlueCore4-External can detect when VBUS is powered up. BlueCore4-External will not pull USB_DP high when VBUS is off. Self powered USB designs (powered from a battery or PSU) must ensure that a PIO line is allocated for USB pull-up purposes. A 1.5K 5% pull-up resistor between USB_DP and the selected PIO line should be fitted to the design. Failure to fit this resistor may result in the design failing to be USB compliant in self powered mode. The internal pull-up in BlueCore is only suitable for bus powered USB devices i.e. dongles. www..com
BlueCore4-External
_aiEceEQJbniEea~a Product Data Sheet
PIO USB_DP
1.5K 5% Rs D+ Rs DRvb1 VBUS Rvb2
USB_DN USB_ON
GND
Figure 11.15: USB Connections for Self Powered Mode
The terminal marked USB_ON can be any free PIO pin. The PIO pin selected must be registered by setting PSKEY_USB_PIO_VBUS to the corresponding pin number.
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11.6.5 Bus Powered Mode
In bus powered mode the application circuit draws its current from the 5V VBUS supply on the USB cable. BlueCore4-External negotiates with the PC during the USB enumeration stage about how much current it is allowed to consume. For Class 2 Bluetooth applications, CSR recommends that the regulator used to derive 3.3V from VBUS is rated at 100mA average current and should be able to handle peaks of 120mA without foldback or limiting. In bus powered mode, BlueCore4-External requests 100mA during enumeration. For Class 1 Bluetooth applications, the USB power descriptor should be altered to reflect the amount of power required. This is accomplished by setting the PS Key PSKEY_USB_MAX_POWER (0x2c6). This is higher than www..coma Class 2 application due to the extra current drawn by the Transmit RF PA. for When selecting a regulator, be aware that VBUS may go as low as 4.4V. The inrush current (when charging reservoir and supply decoupling capacitors) is limited by the USB specification (see USB specification v1.1, Section 7.2.4.1). Some applications may require soft start circuitry to limit inrush current if more than 10F is present between VBUS and GND. The 5V VBUS line emerging from a PC is often electrically noisy. As well as regulation down to 3.3V and 1.8V, applications should include careful filtering of the 5V line to attenuate noise that is above the voltage regulator bandwidth. Excessive noise on the 1.8V supply to the analogue supply pins of BlueCore4-External will result in reduced receive sensitivity and a distorted RF transmit signal.
BlueCore4-External Rs USB_DP Rs USB_DN Rvb1 USB_ON VBUS DD+
_aiEceEQJbniEea~a Product Data Sheet
GND
Voltage Regulator
Figure 11.16: USB Connections for Bus Powered Mode
Note:
USB_ON is shared with BlueCore4-External PIO terminals
Identifier Value Function
Rs Rvb1 Rvb2
27 nominal 22k 5% 47k 5%
Impedance matching to USB cable VBUS ON sense divider VBUS ON sense divider
Table 11.9: USB Interface Component Values
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11.6.6 Suspend Current
All USB devices must permit the USB controller to place them in a USB Suspend mode. While in USB Suspend, bus powered devices must not draw more than 0.5mA from USB VBUS (self powered devices may draw more than 0.5mA from their own supply). This current draw requirement prevents operation of the radio by bus powered devices during USB Suspend. The voltage regulator circuit itself should draw only a small quiescent current (typically less than 100A) to ensure adherence to the suspend current requirement of the USB specification. This is not normally a problem with modern regulators. Ensure that external LEDs and/or amplifiers can be turned off by BlueCore4-External. The entire circuit must be able to enter the suspend mode. (For more details on USB Suspend, see separate CSR documentation).
_aiEceEQJbniEea~a Product Data Sheet
www..com
11.6.7 Detach and Wake-Up Signalling
BlueCore4-External can provide out-of-band signalling to a host controller by using the control lines called `USB_DETACH' and `USB_WAKE_UP'. These are outside the USB specification (no wires exist for them inside the USB cable), but can be useful when embedding BlueCore4-External into a circuit where no external USB is visible to the user. Both control lines are shared with PIO pins and can be assigned to any PIO pin by setting the PS Keys PSKEY_USB_PIO_DETACH and PSKEY_USB_PIO_WAKEUP to the selected PIO number. USB_DETACH is an input which, when asserted high, causes BlueCore4-External to put USB_DN and USB_DP in a high impedance state and turned off the pull-up resistor on D+. This detaches the device from the bus and is logically equivalent to unplugging the device. When USB_DETACH is taken low, BlueCore4-External will connect back to USB and await enumeration by the USB host. USB_WAKE_UP is an active high output (used only when USB_DETACH is active) to wake up the host and allow USB communication to recommence. It replaces the function of the software USB WAKE_UP message (which runs over the USB cable), and cannot be sent while BlueCore4-External is effectively disconnected from the bus.
10ms max 10ms max
USB_DETACH 10ms max No max
USB_WAKE_UP
Port_Impedance USB_DP USB_DN USB_PULL_UP Disconnected
Figure 11.17: USB_DETACH and USB_WAKE_UP Signal
11.6.8 USB Driver
A USB Bluetooth device driver is required to provide a software interface between BlueCore4-External and Bluetooth software running on the host computer. Suitable drivers are available from www.csrsupport.com.
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11.6.9 USB 1.1 Compliance
BlueCore4-External is qualified to the USB specification v1.1, details of which are available from http://www.usb.org. The specification contains valuable information on aspects such as PCB track impedance, supply inrush current and product labelling. Although BlueCore4-External meets the USB specification, CSR cannot guarantee that an application circuit designed around the chip is USB compliant. The choice of application circuit, component choice and PCB layout all affect USB signal quality and electrical characteristics. The information in this document is intended as a guide and should be read in association with the USB specification, with particular attention being given to Chapter 7. Independent USB qualification must be sought before an application is deemed USB compliant and can bear the USB logo. Such qualification can be obtained from a USB plugfest or from an independent USB test house.
_aiEceEQJbniEea~a Product Data Sheet
www..com
Terminals USB_DP and USB_DN adhere to the USB specification 2.0 (Chapter 7) electrical requirements.
11.6.10 USB 2.0 Compatibility
BlueCore4-External is compatible with USB v2.0 host controllers; under these circumstances the two ends agree the mutually acceptable rate of 12Mbits/s according to the USB v2.0 specification.
11.7
Serial Peripheral Interface
BlueCore4-External uses 16-bit data and 16-bit address serial peripheral interface, where transactions may occur when the internal processor is running or is stopped. This section details the considerations required when interfacing to BlueCore4-External via the four dedicated serial peripheral interface terminals. Data may be written or read one word at a time or the auto increment feature may be used to access blocks.
11.7.1 Instruction Cycle
The BlueCore4-External is the slave and receives commands on SPI_MOSI and outputs data on SPI_MISO. The instruction cycle for a SPI transaction is shown in Table 11.10. 1 2 3 4 5 Reset the SPI interface Write the command word Write the address Write or read data words Termination Hold SPI_CSB high for two SPI_CLK cycles Take SPI_CSB low and clock in the 8 bit command Clock in the 16-bit address word Clock in or out 16-bit data word(s) Take SPI_CSB high
Table 11.10: Instruction Cycle for an SPI Transaction
With the exception of reset, SPI_CSB must be held low during the transaction. Data on SPI_MOSI is clocked into the BlueCore4-External on the rising edge of the clock line SPI_CLK. When reading, BlueCore4-External will reply to the master on SPI_MISO with the data changing on the falling edge of the SPI_CLK. The master provides the clock on SPI_CLK. The transaction is terminated by taking SPI_CSB high. Sending a command word and the address of a register for every time it is to be read or written is a significant overhead, especially when large amounts of data are to be transferred. To overcome this BlueCore4-External offers increased data transfer efficiency via an auto increment operation. To invoke auto increment, SPI_CSB is kept low, which auto increments the address, while providing an extra 16 clock cycles for each extra word to be written or read.
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11.7.2 Writing to BlueCore4-External
To write to BlueCore4-External, the 8-bit write command (00000010) is sent first (C[7:0]) followed by a 16-bit address (A[15:0]). The next 16-bits (D[15:0]) clocked in on SPI_MOSI are written to the location set by the address (A). Thereafter for each subsequent 16-bits clocked in, the address (A) is incremented and the data written to consecutive locations until the transaction terminates when SPI_CSB is taken high.
Reset Write_Command SPI_CSB Address(A) Data(A) Data(A+1) etc
End of Cycle
_aiEceEQJbniEea~a Product Data Sheet
www..com
SPI_CLK
SPI_MOSI
C7
C6
C1
C0
A15
A14
A1
A0
D15
D14
D1
D0
D15
D14
D1
D0
D15
D14
D1
D0
Don't Care
SPI_MISO
Processor State
MISO Not Defined During Write
Processor State
Figure 11.18: Write Operation
11.7.3 Reading from BlueCore4-External
Reading from BlueCore4-External is similar to writing to it. An 8-bit read command (00000011) is sent first (C[7:0]), followed by the address of the location to be read (A[15:0]). BlueCore4-External then outputs on SPI_MISO a check word during T[15:0] followed by the 16-bit contents of the addressed location during bits D[15:0]. The check word is composed of {command, address [15:8]}. The check word may be used to confirm a read operation to a memory location. This overcomes the problems encountered with typical serial peripheral interface slaves, whereby it is impossible to determine whether the data returned by a read operation is valid data or the result of the slave device not responding. If SPI_CSB is kept low, data from consecutive locations is read out on SPI_MISO for each subsequent 16 clocks, until the transaction terminates when SPI_CSB is taken high.
Reset Read_Command SPI_CSB Address(A) Check_Word Data(A) Data(A+1) etc End of Cycle
SPI_CLK
SPI_MOSI
C7
C6
C1
C0 A15 A14
A1
A0
Don't Care
SPI_MISO
Processor State
MISO Not Defined During Address
T15 T14
T1
T0
D15 D14
D1
D0 D15 D14
D1
D0
D15 D14
D1
D0
Processor State
Figure 11.19: Read Operation
11.7.4 Multi Slave Operation
BlueCore4-External should not be connected in a multi slave arrangement by simple parallel connection of slave MISO lines. When BlueCore4-External is deselected (SPI_CSB = 1), the SPI_MISO line does not float, instead, BlueCore4-External outputs 0 if the processor is running or 1 if it is stopped.
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11.8
PCM Interface
Pulse Code Modulation (PCM) is a standard method used to digitise audio (particularly voice) patterns for transmission over digital communication channels. Through its PCM interface, BlueCore4-External has hardware support for continual transmission and reception of PCM data, thus reducing processor overhead for wireless headset applications. BlueCore4-External offers a bi directional digital audio interface that routes directly into the baseband layer of the on chip firmware. It does not pass through the HCI protocol layer. Hardware on BlueCore4-External allows the data to be sent to and received from a SCO connection. Up to three SCO connections can be supported by the PCM interface at any one time .
(1)
_aiEceEQJbniEea~a Product Data Sheet
www..com BlueCore4-External can operate as the PCM interface Master generating an output clock of 128, 256 or 512kHz.
When configured as PCM interface slave it can operate with an input clock up to 2048kHz. BlueCore4-External is compatible with a variety of clock formats, including Long Frame Sync, Short Frame Sync and GCI timing environments. It supports 13 or 16-bit linear, 8-bit -law or A-law companded sample formats at 8ksamples/s and can receive and transmit on any selection of three of the first four slots following PCM_SYNC. The PCM configuration options are enabled by setting the PS Key PS KEY_PCM_CONFIG32 (0x1b3). BlueCore4-External interfaces directly to PCM audio devices including the following: Qualcomm MSM 3000 series and MSM 5000 series CDMA baseband devices OKI MSM7705 four channel A-law and -law CODEC Motorola MC145481 8-bit A-law and -law CODEC Motorola MC145483 13-bit linear CODEC STW 5093 and 5094 14-bit linear CODECs BlueCore4-External is also compatible with the Motorola SSITM interface
Note:
(1)
Subject to firmware support, contact CSR for current status.
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Device Terminal Descriptions
11.8.1 PCM Interface Master/Slave
When configured as the Master of the PCM interface, BlueCore4-External generates PCM_CLK and PCM_SYNC.
BlueCore4-External
PCM_OUT PCM_IN
www..com
_aiEceEQJbniEea~a Product Data Sheet
PCM_CLK PCM_SYNC
128/256/512kHz 8kHz
Figure 11.20: BlueCore4-External as PCM Interface Master
When configured as the Slave of the PCM interface, BlueCore4-External accepts PCM_CLK rates up to 2048kHz.
BlueCore4-External
PCM_OUT PCM_IN PCM_CLK PCM_SYNC Upto 2048kHz 8kHz
Figure 11.21: BlueCore4-External as PCM Interface Slave
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11.8.2 Long Frame Sync
Long Frame Sync is the name given to a clocking format that controls the transfer of PCM data words or samples. In Long Frame Sync, the rising edge of PCM_SYNC indicates the start of the PCM word. When BlueCore4-External is configured as PCM Master, generating PCM_SYNC and PCM_CLK, then PCM_SYNC is 8-bits long. When BlueCore4-External is configured as PCM Slave, PCM_SYNC may be from two consecutive falling edges of PCM_CLK to half the PCM_SYNC rate, i.e. 62.5s long.
PCM_SYNC
PCM_CLK
_aiEceEQJbniEea~a Product Data Sheet
www..com
PCM_OUT 1 2 3 4 5 6 7 8
PCM_IN
Undefined
1
2
3
4
5
6
7
8
Undefined
Figure 11.22: Long Frame Sync (Shown with 8-bit Companded Sample)
BlueCore4-External samples PCM_IN on the falling edge of PCM_CLK and transmits PCM_OUT on the rising edge. PCM_OUT may be configured to be high impedance on the falling edge of PCM_CLK in the LSB position or on the rising edge.
11.8.3 Short Frame Sync
In Short Frame Sync the falling edge of PCM_SYNC indicates the start of the PCM word. PCM_SYNC is always one clock cycle long.
PCM_SYNC
PCM_CLK
PCM_OUT
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
PCM_IN
Undefined
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
Undefined
Figure 11.23: Short Frame Sync (Shown with 16-bit Sample)
As with Long Frame Sync, BlueCore4-External samples PCM_IN on the falling edge of PCM_CLK and transmits PCM_OUT on the rising edge. PCM_OUT may be configured to be high impedance on the falling edge of PCM_CLK in the LSB position or on the rising edge.
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Device Terminal Descriptions
11.8.4 Multi Slot Operation
More than one SCO connection over the PCM interface is supported using multiple slots. Up to three SCO connections can be carried over any of the first four slots.
LONG_PCM_SYNC Or SHORT_PCM_SYNC
www..com
PCM_CLK
_aiEceEQJbniEea~a Product Data Sheet
PCM_OUT
1
2
3
4
5
6
78
1
2
3
4
5
6
7
8
PCM_IN
Do Not Care 1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8 Do Not Care
Figure 11.24: Multi Slot Operation with Two Slots and 8-bit Companded Samples
11.8.5 GCI Interface
BlueCore4-External is compatible with the General Circuit Interface, a standard synchronous 2B+D ISDN timing interface. The two 64Kbps B channels can be accessed when this mode is configured.
PCM_SYNC
PCM_CLK
PCM_OUT
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
PCM_IN
Do Not C a re
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
Do Not C a re
B1 Channel
B2 Channel
Figure 11.25: GCI Interface
The start of frame is indicated by the rising edge of PCM_SYNC and runs at 8kHz. With BlueCore4-External in Slave mode, the frequency of PCM_CLK can be up to 4.096MHz.
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Device Terminal Descriptions
11.8.6 Slots and Sample Formats
BlueCore4-External can receive and transmit on any selection of the first four slots following each sync pulse. Slot durations can be either 8 or 16 clock cycles. Duration's of 8 clock cycles may only be used with 8-bit sample formats. Durations of 16 clocks may be used with 8, 13 or 16-bit sample formats. BlueCore4-External supports 13-bit linear, 16-bit linear and 8-bit -law or A-law sample formats. The sample rate is 8ksamples/s. The bit order may be little or big Endian. When 16-bit slots are used, the 3 or 8 unused bits in each slot may be filled with sign extension, padded with zeros or a programmable 3-bit audio attenuation compatible with some Motorola CODECs.
Sign Extension PCM_OUT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
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8-Bit Sample A 16-bit slot with 8-bit companded sample and sign extension selected.
8-Bit Sample PCM_OUT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Zeros Padding A 16-bit slot with 8-bit companded sample and zeros padding selected.
Sign Extension PCM_OUT 1 2 3 4 5 6 7 8 9 10 13-Bit Sample A 16-bit slot with 13-bit linear sample and sign extension selected. 11 12 13 14 15 16
13-Bit Sample PCM_OUT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Audio Gain A 16-bit slot with 13-bit linear sample and audio gain selected. 16
Figure 11.26: 16-Bit Slot Length and Sample Formats
11.8.7 Additional Features
BlueCore4-External has a mute facility that forces PCM_OUT to be 0. In Master mode, PCM_SYNC may also be forced to 0 while keeping PCM_CLK running which some CODECS use to control power down.
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Device Terminal Descriptions
11.8.8 PCM Timing Information
Symbol Parameter Min Typ Max Unit
4MHz DDS generation. Selection of frequency is programmable, see Table 11.13 fmclk PCM_CLK frequency 48MHz DDS generation. Selection of frequency is programmable, see Table 11.14 and Section 11.8.10 4MHz DDS generation 4MHz DDS generation 48MHz DDS generation
128 256 512 kHz
2.9
-
kHz
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tmclkh tmclkl tdmclksynch tdmclkpout tdmclklsyncl tdmclkhsyncl tdmclklpoutz tdmclkhpoutz tsupinclkl thpinclkl
(1) (1)
PCM_SYNC frequency PCM_CLK high PCM_CLK low PCM_CLK jitter
980 730
8 21 -
kHz ns ns ns pk-pk ns ns ns ns ns ns ns ns
Delay time from PCM_CLK high to PCM_SYNC high Delay time from PCM_CLK high to valid PCM_OUT Delay time from PCM_CLK low to PCM_SYNC low (Long Frame Sync only) Delay time from PCM_CLK high to PCM_SYNC low Delay time from PCM_CLK low to PCM_OUT high impedance Delay time from PCM_CLK high to PCM_OUT high impedance Set-up time for PCM_IN valid to PCM_CLK low Hold time for PCM_CLK low to PCM_IN invalid
30 10
-
20 20 20 20 20 20 -
Table 11.11: PCM Master Timing
Note:
(1)
Assumes normal system clock operation. Figures will vary during low power modes, when system clock speeds are reduced.
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Device Terminal Descriptions
t t PCM_SYNC
dmclksynch
dmclklsyncl
t
dmclkhsyncl
f t
mclkh
mlk
t
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mclkl
_aiEceEQJbniEea~a Product Data Sheet
PCM_CLK
t t PCM_OUT
dmclkpout
dmclklpoutz
t ,t
r
f
t LSB (MSB)
dmclkhpoutz
MSB (LSB)
t PCM_IN
supinclkl
t
hpinclkl
MSB (LSB)
LSB (MSB)
Figure 11.27: PCM Master Timing Long Frame Sync
t dmclksynch PCM_SYNC t dmclkhsyncl
fmlk t mclkh PCM_CLK t mclkl
t dmclklpoutz t dmclkpout PCM_OUT MSB (LSB) tr ,t f LSB (MSB) t dmclkhpoutz
t supinclkl PCM_IN
t hpinclkl LSB (MSB)
MSB (LSB)
Figure 11.28: PCM Master Timing Short Frame Sync
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Device Terminal Descriptions
11.8.9 PCM Slave Timing
Symbol Parameter Min Typ Max Unit
fsclk fsclk tsclkl tsclkh thsclksynch tsusclksynch
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PCM clock frequency (Slave mode: input) PCM clock frequency (GCI mode) PCM_CLK low time PCM_CLK high time Hold time from PCM_CLK low to PCM_SYNC high Set-up time for PCM_SYNC high to PCM_CLK low Delay time from PCM_SYNC or PCM_CLK whichever is later, to valid PCM_OUT data (Long Frame Sync only) Delay time from CLK high to PCM_OUT valid data Delay time from PCM_SYNC or PCM_CLK low, whichever is later, to PCM_OUT data line high impedance Set-up time for PCM_IN valid to CLK low Hold time for PCM_CLK low to PCM_IN invalid
Table 11.12: PCM Slave Timing
64 128 200 200 30 30 30 30
-
2048 4096 20 20 20 -
kHz kHz ns ns ns ns
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tdpout tdsclkhpout tdpoutz tsupinsclkl thpinsclkl
ns ns ns ns ns
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Device Terminal Descriptions
f t PCM_CLK
sclkh
sclk
t
tsclkl
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t
hsclksynch
t
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susclksynch
PCM_SYNC
t t PCM_OUT
dpout
dpoutz
t
dsclkhpout
t ,t
r
f
t
dpoutz
MSB (LSB)
LSB (MSB)
t PCM_IN
supinsclkl
t
hpinsclkl
MSB (LSB)
LSB (MSB)
Figure 11.29: PCM Slave Timing Long Frame Sync
fsclk t sclkh PCM_CLK t tsclkl
t susclksynch PCM_SYNC
t hsclksynch
t dsclkhpout PCM_OUT MSB (LSB)
tr ,t f LSB (MSB)
t dpoutz
t dpoutz
t supinsclkl PCM_IN
t hpinsclkl LSB (MSB)
MSB (LSB)
Figure 11.30: PCM Slave Timing Short Frame Sync
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Device Terminal Descriptions
11.8.10 PCM_CLK and PCM_SYNC Generation
BlueCore4-External has two methods of generating PCM_CLK and PCM_SYNC in master mode. The first is generating these signals by Direct Digital Synthesis (DDS) from BlueCore4-External internal 4MHz clock. Using this mode limits PCM_CLK to 128, 256 or 512kHz and PCM_SYNC to 8kHz. The second is generating PCM_CLK and PCM_SYNC by DDS from an internal 48MHz clock which allows a greater range of frequencies to be generated with low jitter but consumes more power. This second method is selected by setting bit `48M_PCM_CLK_GEN_EN' in PSKEY_PCM_CONFIG32. When in this mode and with long frame sync, the length of PCM_SYNC can be either 8 or 16 cycles of PCM_CLK, determined by `LONG_LENGTH_SYNC_EN' in PSKEY_PCM_CONFIG32. The Equation 11.8 describes PCM_CLK frequency when being generated using the internal 48MHz clock:
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f=
CNT _ RATE x 24MHz CNT _ LIMIT
Equation 11.8: PCM_CLK Frequency When Being Generated Using the Internal 48MHz clock
The frequency of PCM_SYNC relative to PCM_CLK can be set using following equation:
f=
PCM _ CLK SYNC _ LIMIT x 8
Equation 11.9: PCM_SYNC Frequency Relative to PCM_CLK
CNT_RATE, CNT_LIMIT and SYNC_LIMIT are set using PSKEY_PCM_LOW_JITTER_CONFIG. As an example, to generate PCM_CLK at 512kHz with PCM_SYNC at 8kHz, set PSKEY_PCM_LOW_JITTER_CONFIG to 0x08080177.
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Device Terminal Descriptions
11.8.11 PCM Configuration
The PCM configuration is set using two PS Keys, PSKEY_PCM_CONFIG32 and PSKEY_PCM_LOW_JITTER_CONFIG. The following tables detail these PS Keys. PSKEY_PCM_CONFIG32. The default for this key is 0x00800000 i.e. first slot following sync is active, 13-bit linear voice format, long frame sync and interface master generating 256kHz PCM_CLK from 4MHz internal clock with no tri-stating of PCM_OUT. PSKEY_PCM_LOW_JITTER_CONFIG is described in Table 11.14.
Name Bit Position Description
SLAVE_MODE_EN
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0 1
Set to 0. 0 selects Master mode with internal generation of PCM_CLK and PCM_SYNC. 1 selects Slave mode requiring externally generated PCM_CLK and PCM_SYNC. This should be set to 1 if 48M_PCM_CLK_GEN_EN (bit 11) is set. 0 selects long frame sync (rising edge indicates start of frame), 1 selects short frame sync (falling edge indicates start of frame). Set to 0. 0 selects padding of 8 or 13-bit voice sample into a 16bit slot by inserting extra LSBs, 1 selects sign extension. When padding is selected with 13-bit voice sample, the 3 padding bits are the audio gain setting; with 8-bit samples the 8 padding bits are zeroes. 0 transmits and receives voice samples MSB first, 1 uses LSB first. 0 drives PCM_OUT continuously, 1 tri-states PCM_OUT immediately after the falling edge of PCM_CLK in the last bit of an active slot, assuming the next slot is not active. 0 tristates PCM_OUT immediately after the falling edge of PCM_CLK in the last bit of an active slot, assuming the next slot is also not active. 1 tristates PCM_OUT after the rising edge of PCM_CLK. 0 enables PCM_SYNC output when master, 1 suppresses PCM_SYNC whilst keeping PCM_CLK running. Some CODECS utilise this to enter a low power state. 1 enables GCI mode. 1 forces PCM_OUT to 0. 0 sets PCM_CLK and PCM_SYNC generation via DDS from internal 4 MHz clock, as for BlueCore4-External. 1 sets PCM_CLK and PCM_SYNC generation via DDS from internal 48 MHz clock. 0 sets PCM_SYNC length to 8 PCM_CLK cycles and 1 sets length to 16 PCM_CLK cycles. Only applies for long frame sync and with 48M_PCM_CLK_GEN_EN set to 1. Set to 0b00000. Selects 128 (0b01), 256 (0b00), 512 (0b10) kHz PCM_CLK frequency when master and 48M_PCM_CLK_GEN_EN (bit 11) is low. Default is `0001'. Ignored by firmware. Selects between 13 (0b00), 16 (0b01), 8 (0b10) bit sample with 16 cycle slot duration or 8 (0b11) bit sample with 8 cycle slot duration.
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SHORT_SYNC_EN
2
SIGN_EXTEND_EN
3 4
LSB_FIRST_EN TX_TRISTATE_EN
5 6
TX_TRISTATE_RISING_EDGE_EN
7
SYNC_SUPPRESS_EN
8
GCI_MODE_EN MUTE_EN 48M_PCM_CLK_GEN_EN
9 10 11
LONG_LENGTH_SYNC_EN
12
MASTER_CLK_RATE
[20:16] [22:21]
ACTIVE_SLOT SAMPLE_FORMAT
[26:23] [28:27]
Table 11.13: PSKEY_PCM_CONFIG32 Description
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Device Terminal Descriptions
Name
Bit Position
Description
CNT_LIMIT CNT_RATE SYNC_LIMIT
[12:0] [23:16] [31:24]
Sets PCM_CLK counter limit. Sets PCM_CLK count rate. Sets PCM_SYNC division relative to PCM_CLK.
Table 11.14: PSKEY_PCM_LOW_JITTER_CONFIG Description
11.9
I/O Parallel Ports
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Fifteen lines of programmable bi-directional input/outputs (I/O) are provided. PIO[11:8] and PIO[3:0] are powered from VDD_PIO. PIO[7:4] are powered from VDD_PADS. AIO [2:0] are powered from VDD_MEM. PIO lines can be configured through software to have either weak or strong pull-ups or pull-downs. All PIO lines are configured as inputs with weak pull-downs at reset. PIO[0] and PIO[1] are normally dedicated to RXEN and TXEN respectively, but they are available for general use. Any of the PIO lines can be configured as interrupt request lines or as wake-up lines from sleep modes. PIO[6] or PIO [2] can be configured as a request line for an external clock source. This is useful when the clock to BlueCore4-External is provided from a system application specific integrated circuit (ASIC). BlueCore4-External has three general purpose analogue interface pins, AIO[0], AIO[1] and AIO[2]. These are used to access internal circuitry and control signals. One pin is allocated to decoupling for the on-chip band gap reference voltage, the other three may be configured to provide additional functionality. Auxiliary functions available via these pins include an 8-bit ADC and an 8-bit DAC. Typically the ADC is used for battery voltage measurement. Signals selectable at these pins include the band gap reference voltage and a variety of clock signals; 48, 24, 16, 8MHz and the XTAL clock frequency. When used with analogue signals the voltage range is constrained by the analogue supply voltage (1.8V). When configured to drive out digital level signals (clocks) generated from within the analogue part of the device, the output voltage level is determined by VDD_MEM (1.8V).
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11.9.1 PIO Defaults for BTv1.2 HCI Level Bluetooth Stack
I/O Terminal Description
PIO[0] PIO[1] PIO[2] PIO[3] PIO[4] PIO[5] PIO[6] PIO[7] AIO[0] AIO[2]
Pull high on boot up to select USB transport rather than BCSP Control output for external LNA after boot up completion Pull high on boot up to select 16MHz reference clock frequency rather than 26MHz Control output for external PA (Class 1 operation) after boot up completion Clock request output Clock request "OR" gate input UART Bypass (UART_TX) UART Bypass (UART_RTS) UART Bypass (UART_CTS) UART Bypass (UART_RX) 32kHz watchdog input Vref output. Must be decoupled
Table 11.15: PIO Defaults
Important Note:
CSR cannot guarantee that these terminal functions remain the same. Please refer to the software release note for the implementation of these PIO lines, as they are firmware build specific.
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Device Terminal Descriptions
11.10
I2C Interface
2
PIO[8:6] can be used to form a Master I C interface. The interface is formed using software to drive these lines. Therefore it is suited only to relatively slow functions such as driving a dot matrix liquid crystal display (LCD), keyboard scanner or EEPROM.
Note:
PIO[7:6] dual functions, UART bypass and EEPROM support, therefore devices using an EEPROM cannot support UART bypass mode PIO lines need to be pulled-up through 2.2k resistors.
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For connection to EEPROMs, refer to CSR documentation on I C EEPROMS for use with BlueCore. This provides information on the type of devices which are currently supported.
+1.8V
2
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10nF 2.2K 2.2K 2.2K U2 8 PIO[8] PIO[6] PIO[7] 7 6 5 VCC WP SCL SDA A0 A1 A2 GND 1 2 3 4
Serial EEPROM (AT24C16A)
Figure 11.31: Example EEPROM Connection
11.11
TCXO Enable OR Function
An OR function exists for clock enable signals from a host controller and BlueCore4-External where either device can turn on the clock without having to wake up the other device. PIO[3] can be used as the Host clock enables input and PIO[2] can be used as the OR output with the TCXO enable signal from BlueCore4-External.
VDD GSM System TCXO CLK IN Enable CLK REQ OUT
BlueCore System CLK REQ IN/ PIO[3] XTAL IN CLK REQ OUT/ PIO[2]
Figure 11.32: Example TXCO Enable OR Function
On reset and up to the time the PIO has been configured, PIO[2] will be tri-stated. Therefore, the developer must ensure that the circuitry connected to this pin is pulled via a 470k resistor to the appropriate power rail. This ensures that the TCXO is oscillating at start up.
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Device Terminal Descriptions
11.12
RESETB
BlueCore4-External may be reset from several sources: RESETB pin, power on reset, a UART break character or via a software configured watchdog timer. The RESETB pin is an active low reset and is internally filtered using the internal low frequency clock oscillator. A reset will be performed between 1.5 and 4.0ms following RESETB being active. It is recommended that RESETB be applied for a period greater than 5ms. The power on reset occurs when the VDD_CORE supply falls below typically 1.5V and is released when VDD_CORE rises above typically 1.6V. At reset the digital I/O pins are set to inputs for bi-directional pins and outputs are tri-stated. The PIOs have weak www..com pull-downs. Following a reset, BlueCore4-External assumes the maximum XTAL_IN frequency, which ensures that the internal clocks run at a safe (low) frequency until BlueCore4-External is configured for the actual XTAL_IN frequency. If no clock is present at XTAL_IN, the oscillator in BlueCore4-External free runs, again at a safe frequency.
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11.12.1 Pin States on Reset
Table 11.16 shows the pin states of BlueCore4-External on reset.
Pin Name State: BlueCore4-External
PIO[11:0] PCM_OUT PCM_IN PCM_SYNC PCM_CLK UART_TX UART_RX UART_RTS UART_CTS USB_DP USB_DN SPI_CSB SPI_CLK SPI_MOSI SPI_MISO AIO[2:0] RESET RESETB TEST_EN TX_A TX_B RF_IN XTAL_IN XTAL_OUT
Input with weak pull-down Tri-stated with weak pull-down Input with weak pull-down Input with weak pull-down Input with weak pull-down Output tri-stated with weak pull-up Input with weak pull-down Output tri-stated with weak pull-up Input with weak pull-down Input with weak pull-down Input with weak pull-down Input with weak pull-up Input with weak pull-down Input with weak pull-down Output tri-stated with weak pull-down Output, driving low Input with weak pull-down Input with weak pull-up Input with strong pull-down High impedance High impedance High impedance High impedance, 250k to XTAL_OUT High impedance, 250k to XTAL_IN
Table 11.16: Pin States of BlueCore4-External on Reset
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Device Terminal Descriptions
11.12.2 Status after Reset
The chip status after a reset is as follows: Warm Reset: Baud rate and RAM data remain available Cold Reset : Baud rate and RAM data not available
Note:
(1) (1)
Cold Reset consititutes one of the following: Power cycle
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System reset (firmware fault code) Reset signal, see Section 11.12
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11.13
Power Supply
11.13.1 Voltage Regulator
An on-chip linear voltage regulator can be used to power the 1.8V dependent supplies. It is advised that a smoothing circuit using a 2.2F low ESR capacitor and 2.2 resistor be placed on the output VDD_ANA adjacent to VREG_IN. The regulator is switched into a low power mode when the device is sent into deep sleep mode. When the on chip regulator is not required VDD_ANA is a 1.8V input and VREG_IN must be either open circuit or tied to VDD_ANA. An on chip linear voltage regulator can be used to power the 1.8V dependent supplies. The regulator is switched into a low power mode when the device is sent into deep sleep mode. When the on chip regulator is not required VDD_ANA is a 1.8V input and VREG_IN must be either open circuit or tied to VDD_ANA.
11.13.2 Sequencing
It is recommended that VDD_CORE, VDD_RADIO, VDD_LO and VDD_ANA be powered at the same time. The order of powering supplies for VDD_CORE, VDD_PIO, VDD_PADS and VDD_USB is not important. However if VDD_CORE is not present, all inputs have a weak pull-down irrespective of the reset state.
11.13.3 Sensitivity to Disturbances
It is recommended that if you are supplying BlueCore4-External from an external voltage source that VDD_LO, VDD_ANA and VDD_RADIO should have less than 10mV rms noise levels between 0 to 10MHz. Single tone frequencies are also to be avoided. A simple RC filter is recommended for VDD_CORE as this reduces transients put back onto the power supply rails The remaining supplies VDD_MEM, VDD_PIO, VDD_PADS and VDD_USB can be connected together with the VREG_IN to the 3.3V supply and simply decoupled as shown in Figure 12.1. The transient response of the regulator is also important. At the start of a packet, power consumption will jump to high levels, see average current consumption section. The regulator should have a response time of 20s or less, it is essential that the power rail recovers quickly.
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Application Schematic
12 Application Schematic
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Figure 12.1: Application Circuit for Radio Characteristics Specification with 8 x 8mm VFBGA Package
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Application Schematic
Notes:
Circuit is for PC application circuit C14, L4, C15 filter is for potentially noisy PC motherboard power supply. Less filtering may be necessary depending on actual application U2 voltage detector holds BlueCore4-External in reset if voltage is low enough for 3.3V flash operation to be unreliable. Not required if 1.8V flash used Various alternative components can be used in the place of discrete RF matching circuit, balun and filter. Please refer to CSR example designs
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Package Dimensions
13 Package Dimensions
13.1 8 x 8mm VFBGA 96-Ball Package
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Figure 13.1: BlueCore4-External 96-Ball VFBGA Package Dimensions
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Package Dimensions
13.2
6 x 6mm VFBGA 96-Ball Package
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Figure 13.2: BlueCore4-External 96-Ball VFBGA Package Dimensions
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Solder Profiles
14 Solder Profiles
The soldering profile depends on various parameters necessitating a set up for each application. The data here is given only for guidance on solder re-flow. There are four zones: 1. 2.
Preheat Zone - This zone raises the temperature at a controlled rate, typically 1-2.5C/s. Equilibrium Zone - This zone brings the board to a uniform temperature and also activates the flux. The duration in this zone (typically 2-3 minutes) will need to be adjusted to optimise the out gassing of the flux. Reflow Zone - The peak temperature should be high enough to achieve good wetting but not so high as to cause component discoloration or damage. Excessive soldering time can lead to intermetallic growth which can result in a brittle joint. Cooling Zone - The cooling rate should be fast, to keep the solder grains small which will give a longer lasting joint. Typical rates will be 2-5C/s.
3.
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_aiEceEQJbniEea~a Product Data Sheet
4.
14.1
Solder Re-Flow Profile for Devices with Lead-Free Solder Balls
Composition of the solder ball: Sn 95.5%, Ag 4.0%, Cu 0.5%
Lead Free Reflow Solder Profile 2
300
250
200 Temperature (C)
150
100
50
0 0 50 100 150 200 250 Time (s) 300 350 400 450 500
Figure 14.1: Typical Lead-Free Re-flow Solder Profile
Key features of the profile: Initial Ramp = 1-2.5C/sec to 175C25C equilibrium Equilibrium time = 60 to 180 seconds Ramp to Maximum temperature (250C) = 3C/sec max. Time above liquidus temperature (217C): 45-90 seconds Device absolute maximum reflow temperature: 260C Devices will withstand the specified profile. Lead-free devices will withstand up to 3 reflows to a maximum temperature of 260C.
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Ordering Information
15 Ordering Information
15.1 BlueCore4-External
Package Order Number Type Size Shipment Method
Interface Version
UART and USB
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96-Ball VFBGA (Pb free) 96-Ball VFBGA (Pb free)
8 x 8 x 1mm 6 x 6 x 1mm
Tape and reel Tape and reel
BC417143B-ES-IQN-E BC417143B-ES-IRN-E
(1)
_aiEceEQJbniEea~a Product Data Sheet
UART and USB
(1)
Maximum Order Engineering Sample Quantity
2kpcs Taped and Reeled
Note:
(1)
When BlueCore4-External reaches Production status order numbers will be BC417143B-IQN-E4 and BC417143B-IRN-E4.
Minimum Order Production Quantity
2kpcs Taped and Reeled
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Tape and Reel Information
16 Tape and Reel Information
Tape and reel is in accordance with EIA-481-2.
16.1
Tape Orientation and Dimensions
The general orientation of the BGA in the tape is as shown in Figure 16.1.
Circular Holes
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BGA
User Direction of Feed
Figure 16.1: Tape and Reel Orientation
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Tape and Reel Information
As a detailed example, the diagram shown in Figure 16.2 outlines the dimensions of the tape used for 8x8x1mm VFBGA devices:
4.0 *See Note 1 2.0 *See Note 6 O1.5 MIN 0.30 0.05 O1.5 +0.1/-0.0 R0.25 1.75 0.25
R0.3 MAX
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Bo BGA
7.5 *See Note 6
_aiEceEQJbniEea~a Product Data Sheet
16.0 0.3
Ko
Ao
Direction of feed
12.0
Section A-A
Notes: 1. 10 sprocket hole pitch cumulative tolerance 02. 2. Camber not to exceed 1mm in 100mm. 3. Material: PS + C. 4. Ao and Bo measured as indicated. 5. Ko measured from a plane on the inside bottom of the pocket to the top surface of the carrier. 6. Pocket position relative to sprocket hole measured as true position of pocket, not pocket hole.
Ao = 6.3 mm Bo = 6.3 mm Ko = 1.1 mm
Figure 16.2: Tape Dimensions
The cover tape has a total peel strength of 0.1N to 1.3N. The direction of the pull should be opposite the direction of the carrier tape such that the cover tape makes an angle of between 165 and 180 with the top of the carrier tape. The carrier and/or cover tape should be pulled with a velocity of 30010mm during peeling. Maximum component rotation inside the cavity is 10 in accordance with EIA-481-2. The cavity pitch tolerance (dimension P1) is 0.1mm. The reel is made of high impact injection moulded polystyrene. The carrier tape is made of polystyrene with carbon. The cover tape is made of antistatic polyester film and an antistatic heat activated adhesive coating.
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Tape and Reel Information
16.2
Reel Information
Reel dimensions
(All dimensions in millimeters)
Full Radius,
See Note 1 Access Hole at Slot Location ( 40 mm min.) flange distortion W3 (Includesouter edge) at
D
See Note 1
W2 (Measured at hub)
_aiEceEQJbniEea~a Product Data Sheet
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A
C
(Arbor hole diameter) If present, tape slot in core for tape start: 2.5mm min. width x 10.0mm min. depth
N (Hub diameter, see Note 2,
Table 1))
W1 (Measured at hub)
See Note 1
B
Notes: 1. Drive spokes optional; if used , dimensions B and D shall apply. 2. Maximum weight of reel and contents 13.6kg.
Figure 16.3: Reel Dimensions
Tape Width 16mm
B Min 1.5mm
C 13.0+0.5/-0.2mm
D Min 20.2mm
N Min 50mm
W1 16.4+2.0/-0.0mm
Table 16.1: Reel Dimensions
Reel Diameter, A 330mm Tape Size 16mm W2 Max 22.4mm W3 15.9mm Min 19.4mm Max
Table 16.2: Diameter Dependent Dimensions
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Tape and Reel Information
16.3
Dry Pack Information
The primary packed product is dry packed in accordance with Joint IPC / JEDEC J-STD-033. All materials used in dry packing conform to EIA-541 and EIA-583. Some illustrative views of reel dry packs are shown in Figure 16.4.
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Humidity Indicator Card 10% ~ 30% Desiccant: two units bags each containing 2 units of desiccant Cube of pink foam to protect tape from crushing
_aiEceEQJbniEea~a Product Data Sheet
Desiccant and Humidity Indicator Card are put on the bottom side of the reel.
Position of label on reel.
Caution Label is printed on dry pack bag. Dry pack bag.
Figure 16.4: Tape and Reel Packaging
Devices shipped in dry-pack bags will withstand storage in normal environmental conditions, such as 30C and 70% RH for a minimum of one year as long as the dry-pack bag has not become punctured. Humidity indicators inside the dry-pack bag will confirm this when the bag is opened.
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Tape and Reel Information
16.4
Baking Conditions
Devices may, if necessary, be re-baked at 125C for 24 hours. If devices are still on the reel, which cannot withstand such high temperatures, they should be baked at 45C for 192 hours at relative humidity less than 5%. Solder wettability of parts will be unaffected by three such bakes.
16.5
Product Information
Example product information labels are shown is Figure 16.5.
_aiEceEQJbniEea~a Product Data Sheet
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4
Figure 16.5: Product Information Labels
A product information label is placed on each reel, primary package and shipment package
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Contact Information
17 Contact Information
_aiEceEQJbniEea~a Product Data Sheet
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CSR UK Cambridge Science Park Milton Road Cambridge, CB4 0WH United Kingdom Tel: +44 (0) 1223 692 000 Fax: +44 (0) 1223 692 001 e-mail: sales@csr.com
CSR Denmark Novi Science Park Niels Jernes Vej 10 9220 Aalborg East Denmark Tel: +45 72 200 380 Fax: +45 96 354 599 e-mail: sales@csr.com
CSR Japan CSR KK 9F Kojimachi KS Square 5-3-3, Kojimachi, Chiyoda-ku, Tokyo 102-0083 Japan Tel: +81-3-5276-2911 Fax: +81-3-5276-2915 e-mail: sales@csr.com
CSR Korea Rm. 1111 Keumgang Venturetel, #1108 Beesan-dong, Dong An-ku, Anyang-city, Kyunggi-do 431-050, Korea Tel: +82 31 389 0541 Fax : +82 31 389 0545 e-mail: sales@csr.com
CSR Taiwan Rm6A,6F, No. 118, Hsing-Shan Rd., NeiHu, Taipei, Taiwan, R.O.C. Tel: +886 2 7721 5588 Fax: +886 2 7721 5589 e-mail: sales@csr.com
CSR U.S. 1651 N. Collins Blvd. Suite 210 Richardson TX75080 Tel: +1 (972) 238 2300 Fax: +1 (972) 231 1440 e-mail: sales@csr.com
To contact a CSR representative, go to http://www.csr.com/contacts.htm
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Document References
18 Document References
Document: Reference, Date:
Specification of the Bluetooth System Universal Serial Bus Specification Selection of I C EEPROMS for Use with BlueCore EDR RF Test Specification v0.9 RF Prototyping Specification for Enhanced Data Rate IP
2
v1.2, 05 November 2003 v2.0, 27 April 2000 bcore-an-008Pb, 30 September 2003 v0.90, D07r22, 16 March 2004 v.90, r29, 2004
_aiEceEQJbniEea~a Product Data Sheet
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Acronyms and Definitions
Acronyms and Definitions
8DPSK /4 DQPSK BlueCoreTM BluetoothTM CSR ACL ADC
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8 phase Differential Phase Shift Keying pi/4 rotated Differential Quaternary Phase Shift Keying Group term for CSR's range of Bluetooth chips Set of technologies providing audio and data transfer over short-range radio connections Cambridge Silicon Radio Asynchronous Connection-Less. A Bluetooth data packet. Analogue to Digital Converter Automatic Gain Control Audio encoding standard Application Programming Interface Application Specific Integrated Circuit BlueCoreTM Serial Protocol Bit Error Rate. Used to measure the quality of a link Built-In Self-Test Burst Mode Controller Complementary Metal Oxide Semiconductor Coder Decoder Chip Select (Active Low) Cambridge Silicon Radio Clear to Send Continuous Variable Slope Delta Modulation Digital to Analogue Converter Decibels relative to 1mW Direct Current Differential Error Vector Magnitude Device Firmware Upgrade Differential Phase Shift Keying Differential Quaternary Phase Shift Keying Equivalent Series Resistance Frequency Shift Keying Global System for Mobile communications Host Controller Interface In-Phase and Quadrature Modulation Intermediate Frequency Infinite Impulse Response Integrated Services Digital Network Industrial, Scientific and Medical KiloSamples Per Second Logical Link Control and Adaptation Protocol (protocol layer) Link Controller Liquid Crystal Display Low profile Fine Ball Grid Array Low Noise Amplifier
_aiEceEQJbniEea~a Product Data Sheet
AGC A-law API ASIC BCSP BER BIST BMC CMOS CODEC CSB CSR CTS CVSD DAC dBm DC DEVM DFU DPSK DQPSK ESR FSK GSM HCI IQ Modulation IF IIR ISDN ISM ksps L2CAP LC LCD LFBGA LNA
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Acronyms and Definitions
LPF LSB -law MCU MMU MISO MOSI Mbps OHCI PA www..com PCM PIO PLL ppm PS Key RAM REB REF RF RFCOMM RISC rms RoHS RSSI RTS RX SCO SD SDK SDP SPI TBA TBD TX UART USB VCO VFBGA VM W-CDMA WEB www
Low Pass Filter Least-Significant Bit Audio Encoding Standard MicroController Unit Memory Management Unit Master In Serial Out Master Out Slave In Mega bits per second Open Host Controller Interface Power Amplifier Pulse Code Modulation. Refers to digital voice data Parallel Input Output Phase Lock Loop parts per million Persistent Store Key Random Access Memory Read enable (Active Low) Reference. Represents dimension for reference use only. Radio Frequency Protocol layer providing serial port emulation over L2CAP Reduced Instruction Set Computer root mean squared The Restriction of Hazardous Substances in Electrical and Electronic Equipment Directive (2002/95/EC) Receive Signal Strength Indication Ready To Send Receive or Receiver Synchronous Connection-Oriented. Voice oriented Bluetooth packet Secure Digital Software Development Kit Service Discovery Protocol Serial Peripheral Interface To Be Announced To Be Defined Transmit or Transmitter Universal Asynchronous Receiver Transmitter Universal Serial Bus or Upper Side Band (depending on context) Voltage Controlled Oscillator Very Fine Ball Grid Array Virtual Machine Wideband Code Division Multiple Access Write Enable (Active Low) world wide web
_aiEceEQJbniEea~a Product Data Sheet
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Record of Changes
Record of Changes
Date: Revision Reason for Change:
03 JUN 04 15 JUN 04 06 SEPT 04
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a b c
Original publication of Pre-Production Information Product Data Sheet (CSR reference: BC417143B-ds-001Pa) Numbering changes made to AIO pins. 6 x 6mm package option added to data sheet and AUX DAC removed.
_aiEceEQJbniEea~a Product Data Sheet
BlueCoreTM4-External Product Data Sheet BC417143B-ds-001Pc September 2004
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